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Message-ID: <aebedcca-16a0-64e8-747e-47afae983715@linaro.org> Date: Mon, 7 Aug 2023 08:18:19 +0200 From: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org> To: Radhey Shyam Pandey <radhey.shyam.pandey@....com>, vkoul@...nel.org, robh+dt@...nel.org, krzysztof.kozlowski+dt@...aro.org, conor+dt@...nel.org, michal.simek@....com, davem@...emloft.net, edumazet@...gle.com, kuba@...nel.org, pabeni@...hat.com, linux@...linux.org.uk Cc: dmaengine@...r.kernel.org, devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org, netdev@...r.kernel.org, git@....com Subject: Re: [PATCH net-next v5 08/10] dt-bindings: net: xlnx,axi-ethernet: Introduce DMA support On 07/08/2023 07:51, Radhey Shyam Pandey wrote: > Xilinx 1G/2.5G Ethernet Subsystem provides 32-bit AXI4-Stream buses to > move transmit and receive Ethernet data to and from the subsystem. > > These buses are designed to be used with an AXI Direct Memory Access(DMA) > IP or AXI Multichannel Direct Memory Access (MCDMA) IP core, AXI4-Stream > Data FIFO, or any other custom logic in any supported device. > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org> Best regards, Krzysztof
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