lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
Open Source and information security mailing list archives
| ||
|
Message-ID: <2690985.mvXUDI8C0e@jernej-laptop> Date: Mon, 07 Aug 2023 09:48:42 +0200 From: Jernej Škrabec <jernej.skrabec@...il.com> To: netdev@...r.kernel.org, Marc Kleine-Budde <mkl@...gutronix.de> Cc: davem@...emloft.net, kuba@...nel.org, linux-can@...r.kernel.org, kernel@...gutronix.de, Marc Kleine-Budde <mkl@...gutronix.de> Subject: Re: [PATCH net-next] Revert "riscv: dts: allwinner: d1: Add CAN controller nodes" Dne ponedeljek, 07. avgust 2023 ob 09:42:22 CEST je Marc Kleine-Budde napisal(a): > It turned out the dtsi changes were not quite ready, revert them for > now. > > This reverts commit 6ea1ad888f5900953a21853e709fa499fdfcb317. > > Link: https://lore.kernel.org/all/2690764.mvXUDI8C0e@jernej-laptop > Suggested-by: Jernej Škrabec <jernej.skrabec@...il.com> > Link: > https://lore.kernel.org/all/20230807-riscv-allwinner-d1-revert-can-controll > er-nodes-v1-1-eb3f70b435d9@...gutronix.de Signed-off-by: Marc Kleine-Budde > <mkl@...gutronix.de> Reviewed-by: Jernej Skrabec <jernej.skrabec@...il.com> Best regards, Jernej > --- > .../boot/dts/allwinner/sunxi-d1s-t113.dtsi | 30 ------------------- > 1 file changed, 30 deletions(-) > > diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi > b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi index > 4086c0cc0f9d..1bb1e5cae602 100644 > --- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi > +++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi > @@ -131,18 +131,6 @@ uart3_pb_pins: uart3-pb-pins { > pins = "PB6", "PB7"; > function = "uart3"; > }; > - > - /omit-if-no-ref/ > - can0_pins: can0-pins { > - pins = "PB2", "PB3"; > - function = "can0"; > - }; > - > - /omit-if-no-ref/ > - can1_pins: can1-pins { > - pins = "PB4", "PB5"; > - function = "can1"; > - }; > }; > > ccu: clock-controller@...1000 { > @@ -891,23 +879,5 @@ rtc: rtc@...0000 { > clock-names = "bus", "hosc", "ahb"; > #clock-cells = <1>; > }; > - > - can0: can@...4000 { > - compatible = "allwinner,sun20i-d1-can"; > - reg = <0x02504000 0x400>; > - interrupts = <SOC_PERIPHERAL_IRQ(21) IRQ_TYPE_LEVEL_HIGH>; > - clocks = <&ccu CLK_BUS_CAN0>; > - resets = <&ccu RST_BUS_CAN0>; > - status = "disabled"; > - }; > - > - can1: can@...4400 { > - compatible = "allwinner,sun20i-d1-can"; > - reg = <0x02504400 0x400>; > - interrupts = <SOC_PERIPHERAL_IRQ(22) IRQ_TYPE_LEVEL_HIGH>; > - clocks = <&ccu CLK_BUS_CAN1>; > - resets = <&ccu RST_BUS_CAN1>; > - status = "disabled"; > - }; > }; > }; > > base-commit: c35e927cbe09d38b2d72183bb215901183927c68
Powered by blists - more mailing lists