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Message-ID: <CACRpkdb9H+sQyrBTQBSz8wagtpBVruJj+p+p60hxsfGNbQveUw@mail.gmail.com>
Date: Tue, 15 Aug 2023 08:41:36 +0200
From: Linus Walleij <linus.walleij@...aro.org>
To: "Russell King (Oracle)" <linux@...linux.org.uk>
Cc: Vladimir Oltean <olteanv@...il.com>, Andrew Lunn <andrew@...n.ch>,
Heiner Kallweit <hkallweit1@...il.com>, Florian Fainelli <f.fainelli@...il.com>,
"David S. Miller" <davem@...emloft.net>, Eric Dumazet <edumazet@...gle.com>,
Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>, netdev@...r.kernel.org
Subject: Re: [PATCH net-next] net: dsa: mark parsed interface mode for legacy
switch drivers
On Sun, Aug 13, 2023 at 11:56 PM Linus Walleij <linus.walleij@...aro.org> wrote:
> On Sat, Aug 12, 2023 at 2:16 PM Russell King (Oracle)
> <linux@...linux.org.uk> wrote:
> > So for realtek, I propose (completely untested):
>
> I applied it and it all works fine afterwards on the DIR-685.
> Should I test some different configs in the DTS as well?
I applied the following two patches on top of your patch, and
it works like a charm.
>From e23b281afecd019322fd7d3f0e1c2f561842b02a Mon Sep 17 00:00:00 2001
From: Linus Walleij <linus.walleij@...aro.org>
Date: Tue, 15 Aug 2023 08:21:18 +0200
Subject: [PATCH 1/2] RFC: net: dsa: realtek: Implement setting up link on CPU
port
We auto-negotiate most ports in the RTL8366RB driver, but
the CPU port is hard-coded to 1Gbit, full duplex, tx and
rx pause.
Actually respect the arguments passed to the function for
the CPU port.
After this the link is still set up properly.
Signed-off-by: Linus Walleij <linus.walleij@...aro.org>
---
This patch requires Russell Kings patch:
"net: dsa: realtek: add phylink_get_caps implementation"
---
drivers/net/dsa/realtek/rtl8366rb.c | 42 ++++++++++++++++++++++-------
1 file changed, 33 insertions(+), 9 deletions(-)
diff --git a/drivers/net/dsa/realtek/rtl8366rb.c
b/drivers/net/dsa/realtek/rtl8366rb.c
index 76b5c43e1430..385225980e8d 100644
--- a/drivers/net/dsa/realtek/rtl8366rb.c
+++ b/drivers/net/dsa/realtek/rtl8366rb.c
@@ -95,12 +95,6 @@
#define RTL8366RB_PAACR_RX_PAUSE BIT(6)
#define RTL8366RB_PAACR_AN BIT(7)
-#define RTL8366RB_PAACR_CPU_PORT (RTL8366RB_PAACR_SPEED_1000M | \
- RTL8366RB_PAACR_FULL_DUPLEX | \
- RTL8366RB_PAACR_LINK_UP | \
- RTL8366RB_PAACR_TX_PAUSE | \
- RTL8366RB_PAACR_RX_PAUSE)
-
/* bits 0..7 = port 0, bits 8..15 = port 1 */
#define RTL8366RB_PSTAT0 0x0014
/* bits 0..7 = port 2, bits 8..15 = port 3 */
@@ -1081,6 +1075,7 @@ rtl8366rb_mac_link_up(struct dsa_switch *ds, int
port, unsigned int mode,
int speed, int duplex, bool tx_pause, bool rx_pause)
{
struct realtek_priv *priv = ds->priv;
+ unsigned int val;
int ret;
if (port != priv->cpu_port)
@@ -1088,22 +1083,51 @@ rtl8366rb_mac_link_up(struct dsa_switch *ds,
int port, unsigned int mode,
dev_dbg(priv->dev, "MAC link up on CPU port (%d)\n", port);
- /* Force the fixed CPU port into 1Gbit mode, no autonegotiation */
+ /* Force the fixed CPU port forced, no autonegotiation */
ret = regmap_update_bits(priv->map, RTL8366RB_MAC_FORCE_CTRL_REG,
BIT(port), BIT(port));
if (ret) {
- dev_err(priv->dev, "failed to force 1Gbit on CPU port\n");
+ dev_err(priv->dev, "failed to force CPU port\n");
return;
}
+ /* Conjure port config */
+ switch (speed) {
+ case SPEED_10:
+ val = RTL8366RB_PAACR_SPEED_10M;
+ break;
+ case SPEED_100:
+ val = RTL8366RB_PAACR_SPEED_100M;
+ break;
+ case SPEED_1000:
+ val = RTL8366RB_PAACR_SPEED_1000M;
+ break;
+ default:
+ val = RTL8366RB_PAACR_SPEED_1000M;
+ break;
+ }
+
+ if (duplex == DUPLEX_FULL)
+ val |= RTL8366RB_PAACR_FULL_DUPLEX;
+
+ if (tx_pause)
+ val |= RTL8366RB_PAACR_TX_PAUSE;
+
+ if (rx_pause)
+ val |= RTL8366RB_PAACR_RX_PAUSE;
+
+ val |= RTL8366RB_PAACR_LINK_UP;
+
ret = regmap_update_bits(priv->map, RTL8366RB_PAACR2,
0xFF00U,
- RTL8366RB_PAACR_CPU_PORT << 8);
+ val << 8);
if (ret) {
dev_err(priv->dev, "failed to set PAACR on CPU port\n");
return;
}
+ dev_dbg(priv->dev, "set PAACR to %04x\n", val);
+
/* Enable the CPU port */
ret = regmap_update_bits(priv->map, RTL8366RB_PECR, BIT(port),
0);
--
2.41.0
>From e534aebdd57bbbab3aff56198ffa38f21b752752 Mon Sep 17 00:00:00 2001
From: Linus Walleij <linus.walleij@...aro.org>
Date: Tue, 15 Aug 2023 08:30:13 +0200
Subject: [PATCH 2/2] RFC: ARM: gemini: dir-685: Set switch link to rgmii-id
As concluded from discussions on the mailing lists, this
setting makes no sense. The only reason it worked was because
of hard-coded default handling in the drivers.
Signed-off-by: Linus Walleij <linus.walleij@...aro.org>
---
This patch requires Russell Kings patch
"net: dsa: realtek: add phylink_get_caps implementation"
---
arch/arm/boot/dts/gemini/gemini-dlink-dir-685.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/gemini/gemini-dlink-dir-685.dts
b/arch/arm/boot/dts/gemini/gemini-dlink-dir-685.dts
index 396149664297..778115c4461c 100644
--- a/arch/arm/boot/dts/gemini/gemini-dlink-dir-685.dts
+++ b/arch/arm/boot/dts/gemini/gemini-dlink-dir-685.dts
@@ -237,7 +237,7 @@ rtl8366rb_cpu_port: port@5 {
reg = <5>;
label = "cpu";
ethernet = <&gmac0>;
- phy-mode = "rgmii";
+ phy-mode = "rgmii-id";
fixed-link {
speed = <1000>;
full-duplex;
--
2.41.0
Yours,
Linus Walleij
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