netdev - Re: [RFC net-next v1 3/5] net: phy: nxp-c45-tja11xx add MACsec support

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Message-ID: <a72d3396-7f7b-c9a5-e4b9-e9335e0feba3@oss.nxp.com>
Date: Wed, 16 Aug 2023 11:18:38 +0300
From: "Radu Pirea (OSS)" <radu-nicolae.pirea@....nxp.com>
To: Andrew Lunn <andrew@...n.ch>
Cc: hkallweit1@...il.com, linux@...linux.org.uk, davem@...emloft.net,
 edumazet@...gle.com, kuba@...nel.org, pabeni@...hat.com,
 richardcochran@...il.com, sd@...asysnail.net, netdev@...r.kernel.org,
 linux-kernel@...r.kernel.org
Subject: Re: [RFC net-next v1 3/5] net: phy: nxp-c45-tja11xx add MACsec
 support


On 11.08.2023 20:10, Andrew Lunn wrote:
>> +#define VEND1_MACSEC_BASE		0x9000
>> +
>> +#define MACSEC_CFG			0x0000
>> +#define MACSEC_CFG_BYPASS		BIT(1)
>> +#define MACSEC_CFG_S0I			BIT(0)
>> +
>> +#define MACSEC_TPNET			0x0044
> 
>> +static int nxp_c45_macsec_write(struct phy_device *phydev, u16 reg, u32 val)
>> +{
>> +	reg = reg / 2;
> 
> That is a bit odd. How does the data sheet describe these
> registers. e.g. MACSEC_TPNET. Does it say 0x9022 and 0x9023?  It seems
> it would be easy to mix this up and end up accessing 0x9011 and
> 0x9012.
> 
> 	   Andrew

According to the MACsec IP user manual, the registers are 32 bits wide 
and the addresses are 4 byte aligned. The PHY translates two writes in 
two consecutive registers in one write in the MACsec IP.

I agree. It's too easy to write the wrong address here. I should check 
the address alignment.

-- 
Radu P.