netdev - Re: [PATCH net-next] net: dsa: mark parsed interface mode for legacy switch drivers

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Message-ID: <65657a0e-0b54-4af4-8a38-988b7393a9f5@lunn.ch>
Date: Thu, 17 Aug 2023 20:52:12 +0200
From: Andrew Lunn <andrew@...n.ch>
To: Vladimir Oltean <olteanv@...il.com>
Cc: "Russell King (Oracle)" <linux@...linux.org.uk>,
	Linus Walleij <linus.walleij@...aro.org>,
	Heiner Kallweit <hkallweit1@...il.com>,
	Florian Fainelli <f.fainelli@...il.com>,
	"David S. Miller" <davem@...emloft.net>,
	Eric Dumazet <edumazet@...gle.com>,
	Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>,
	netdev@...r.kernel.org
Subject: Re: [PATCH net-next] net: dsa: mark parsed interface mode for legacy
 switch drivers

> Andrew, I'd argue that the MAC-PHY relationship between the DSA master
> and the CPU port is equally clear as between 2 arbitrary cascade ports.
> Which is: not clear at all. The RGMII standard does not talk about the
> existence of a MAC role and a PHY role, to my knowledge.

The standard does talk about an optional in band status, placed onto
the RXD pins during the inter packet gap. For that to work, there
needs to be some notion of MAC and PHY side.

> With rx-internal-delay-ps and tx-internal-delay-ps in each MAC node, you
> get the freedom of specifying RGMII delays in whichever way is needed,
> without baking in any assumption that the port plays the role of a PHY
> or not.

I agree with you here, but these are modern inventions, as a result of
evolution over time, as we see what does and does not work well, and
as we as developers go from newbies to seasoned developers getting
better at defining consistent APIs.

	Andrew