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Message-ID: <xuy7jenzuseth4rwbvqbpb4db3r6ynzagpcrt37kcme7r4izqq@wltdeqwmybpw> Date: Fri, 18 Aug 2023 19:30:14 +0300 From: Serge Semin <fancer.lancer@...il.com> To: Jisheng Zhang <jszhang@...nel.org> Cc: "David S . Miller" <davem@...emloft.net>, Eric Dumazet <edumazet@...gle.com>, Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>, Rob Herring <robh+dt@...nel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>, Conor Dooley <conor+dt@...nel.org>, Giuseppe Cavallaro <peppe.cavallaro@...com>, Alexandre Torgue <alexandre.torgue@...s.st.com>, Jose Abreu <joabreu@...opsys.com>, netdev@...r.kernel.org, linux-kernel@...r.kernel.org, devicetree@...r.kernel.org, linux-stm32@...md-mailman.stormreply.com, linux-arm-kernel@...ts.infradead.org Subject: Re: [PATCH net-next v5 3/9] net: stmmac: enlarge max rx/tx queues and channels to 16 On Fri, Aug 18, 2023 at 12:57:43AM +0800, Jisheng Zhang wrote: > xgmac supports up to 16 rx/tx queues and up to 16 channels. > > Signed-off-by: Jisheng Zhang <jszhang@...nel.org> > Acked-by: Alexandre TORGUE <alexandre.torgue@...s.st.com> > --- > drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c | 5 ++--- > include/linux/stmmac.h | 6 +++--- > 2 files changed, 5 insertions(+), 6 deletions(-) > > diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c > index 38782662ff98..8ac994553bc1 100644 > --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c > +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c > @@ -232,9 +232,8 @@ static void dwxgmac2_map_mtl_to_dma(struct mac_device_info *hw, u32 queue, > void __iomem *ioaddr = hw->pcsr; > u32 value, reg; > > - reg = (queue < 4) ? XGMAC_MTL_RXQ_DMA_MAP0 : XGMAC_MTL_RXQ_DMA_MAP1; > - if (queue >= 4) > - queue -= 4; > + reg = XGMAC_MTL_RXQ_DMA_MAP0 + (queue & ~0x3); > + queue &= 0x3; > > value = readl(ioaddr + reg); > value &= ~XGMAC_QxMDMACH(queue); > diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h > index 784277d666eb..9c90e2e295d4 100644 > --- a/include/linux/stmmac.h > +++ b/include/linux/stmmac.h > @@ -15,9 +15,9 @@ > #include <linux/platform_device.h> > #include <linux/phy.h> > > -#define MTL_MAX_RX_QUEUES 8 > -#define MTL_MAX_TX_QUEUES 8 > -#define STMMAC_CH_MAX 8 > +#define MTL_MAX_RX_QUEUES 16 In DW XGMAC 2.11a (Databook from 9.2015) number of MTL Rx queues is limited with 12: Number of Receive Queues Description: Specifies the number of receive queues. Value Range: 1–12 Default Value: 1 Dependencies: This option is not available in XGMAC-CORE configurations. HDL Parameter Name: DWCXG_NUM_RXQ Are you sure it's different in your case? Do you have a Synopsys HW manual with the DWCXG_NUM_RXQ parameter range limited to 16? What IP-core version is it about? -Serge(y) > +#define MTL_MAX_TX_QUEUES 16 > +#define STMMAC_CH_MAX 16 > > #define STMMAC_RX_COE_NONE 0 > #define STMMAC_RX_COE_TYPE1 1 > -- > 2.40.1 > >
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