netdev - Re: [RFC PATCH net-next 8/8] dt-bindings: net: fsl,backplane-anlt: new binding document

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Date: Mon, 21 Aug 2023 23:34:33 +0300
From: Vladimir Oltean <vladimir.oltean@....com>
To: Andrew Lunn <andrew@...n.ch>
Cc: Rob Herring <robh@...nel.org>, netdev@...r.kernel.org,
	devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
	linux-phy@...ts.infradead.org,
	"Russell King (Oracle)" <rmk+kernel@...linux.org.uk>,
	Heiner Kallweit <hkallweit1@...il.com>,
	Florian Fainelli <f.fainelli@...il.com>,
	Madalin Bucur <madalin.bucur@....com>,
	Ioana Ciornei <ioana.ciornei@....com>,
	Camelia Groza <camelia.groza@....com>, Li Yang <leoyang.li@....com>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
	Conor Dooley <conor@...nel.org>,
	Sean Anderson <sean.anderson@...o.com>,
	Maxime Chevallier <maxime.chevallier@...tlin.com>,
	Vinod Koul <vkoul@...nel.org>,
	Kishon Vijay Abraham I <kishon@...nel.org>
Subject: Re: [RFC PATCH net-next 8/8] dt-bindings: net: fsl,backplane-anlt:
 new binding document

On Mon, Aug 21, 2023 at 10:20:43PM +0200, Andrew Lunn wrote:
> > > >        - items:
> > > >            - pattern: "^ethernet-phy-id[a-f0-9]{4}\\.[a-f0-9]{4}$"
> > > >            - const: ethernet-phy-ieee802.3-c45
> > > > +      - items:
> > > > +          - const: fsl,lx2160a-backplane-anlt
> > > > +          - const: ethernet-phy-ieee802.3-c45
> > > 
> > > What's the benefit of having ethernet-phy-ieee802.3-c45? Will it work if 
> > > the OS only understands that and not fsl,lx2160a-backplane-anlt?
> > 
> > No. The "is_c45" bool won't get set correctly in fwnode_mdiobus_register_phy().
> > 
> > 	is_c45 = fwnode_device_is_compatible(child, "ethernet-phy-ieee802.3-c45");
> > 
> > With that bool set incorrectly, the MDIO protocol cannot access the device's
> > registers.
> > 
> > > > +        description:
> > > > +          Some C45 PHYs have no PHY ID in the standard location, and there is
> > > > +          also no PHY ID allocated for them to fake. They are identified by the
> > > > +          primary compatible string, plus the secondary one to distinguish them
> > > > +          from a raw MDIO device.
> 
> Could you fake ID registers? Is this on any arbitrary MDIO bus, or an
> internal bus with its own MDIO driver which could trap reads to the ID
> registers and return well known values?
> 
> 	Andrew

The MDIO bus is not arbitrary, the integration choice with this register
layout is specific to the LX2160A SoC, and it's an internal PHY there.

But, there's already something else at those MDIO registers (where the
standard PHY ID location is), in the MMD that the AN/LT block responds to.
And that would be:

/* Auto-Negotiation Control and Status Registers are on page 0: 0x0 */
static const u16 mtip_lx2160a_an_regs[] = {
	[AN_CTRL] = 0,
	[AN_STAT] = 1,
	[AN_ADV_0] = 2, // overlaps with MII_PHYSID1
	[AN_ADV_1] = 3, // overlaps with MII_PHYSID2
	[AN_ADV_2] = 4,
	[AN_LPA_0] = 5, // overlaps with MDIO_DEVS1
	[AN_LPA_1] = 6, // overlaps with MDIO_DEVS2
	[AN_LPA_2] = 7,
	[AN_MS_CNT] = 8,
	[AN_ADV_XNP_0] = 9,
	[AN_ADV_XNP_1] = 10,
	[AN_ADV_XNP_2] = 11,
	[AN_LPA_XNP_0] = 12,
	[AN_LPA_XNP_1] = 13,
	[AN_LPA_XNP_2] = 14,
	[AN_BP_ETH_STAT] = 15,
};

The AN advertisement registers are kinda important to the operation of
the driver, so I wouldn't want to mask them with fake PHY ID values
reported by the MDIO controller.

The other option would be to somehow make the mtip_backplane driver
remap (and thus, standardize) its own register space as phy_read_mmd()
and phy_write_mmd() see it, but it's not clear at all how that would
be done, or if it was done before / would be useful generally.