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Message-Id: <20230824075500.1735790-10-junfeng.guo@intel.com>
Date: Thu, 24 Aug 2023 15:54:54 +0800
From: Junfeng Guo <junfeng.guo@...el.com>
To: intel-wired-lan@...ts.osuosl.org
Cc: netdev@...r.kernel.org,
anthony.l.nguyen@...el.com,
jesse.brandeburg@...el.com,
qi.z.zhang@...el.com,
ivecera@...hat.com,
sridhar.samudrala@...el.com,
horms@...nel.org,
kuba@...nel.org,
edumazet@...gle.com,
davem@...emloft.net,
pabeni@...hat.com,
Junfeng Guo <junfeng.guo@...el.com>
Subject: [PATCH iwl-next v8 09/15] ice: init XLT key builder for parser
Parse below DDP section into struct ice_xlt_kb:
ICE_SID_XLT_KEY_BUILDER_SW
ICE_SID_XLT_KEY_BUILDER_ACL
ICE_SID_XLT_KEY_BUILDER_FD
ICE_SID_XLT_KEY_BUILDER_RSS
Signed-off-by: Junfeng Guo <junfeng.guo@...el.com>
---
drivers/net/ethernet/intel/ice/ice_parser.c | 28 +++
drivers/net/ethernet/intel/ice/ice_parser.h | 9 +
drivers/net/ethernet/intel/ice/ice_xlt_kb.c | 235 ++++++++++++++++++++
drivers/net/ethernet/intel/ice/ice_xlt_kb.h | 79 +++++++
4 files changed, 351 insertions(+)
create mode 100644 drivers/net/ethernet/intel/ice/ice_xlt_kb.c
create mode 100644 drivers/net/ethernet/intel/ice/ice_xlt_kb.h
diff --git a/drivers/net/ethernet/intel/ice/ice_parser.c b/drivers/net/ethernet/intel/ice/ice_parser.c
index 3c3f7d6bea52..6499bb774667 100644
--- a/drivers/net/ethernet/intel/ice/ice_parser.c
+++ b/drivers/net/ethernet/intel/ice/ice_parser.c
@@ -229,6 +229,30 @@ int ice_parser_create(struct ice_hw *hw, struct ice_parser **psr)
goto err;
}
+ p->xlt_kb_sw = ice_xlt_kb_get_sw(hw);
+ if (!p->xlt_kb_sw) {
+ status = -EINVAL;
+ goto err;
+ }
+
+ p->xlt_kb_acl = ice_xlt_kb_get_acl(hw);
+ if (!p->xlt_kb_acl) {
+ status = -EINVAL;
+ goto err;
+ }
+
+ p->xlt_kb_fd = ice_xlt_kb_get_fd(hw);
+ if (!p->xlt_kb_fd) {
+ status = -EINVAL;
+ goto err;
+ }
+
+ p->xlt_kb_rss = ice_xlt_kb_get_rss(hw);
+ if (!p->xlt_kb_rss) {
+ status = -EINVAL;
+ goto err;
+ }
+
*psr = p;
return 0;
err:
@@ -254,6 +278,10 @@ void ice_parser_destroy(struct ice_parser *psr)
devm_kfree(ice_hw_to_dev(psr->hw), psr->mk_grp_table);
devm_kfree(ice_hw_to_dev(psr->hw), psr->proto_grp_table);
devm_kfree(ice_hw_to_dev(psr->hw), psr->flg_rd_table);
+ devm_kfree(ice_hw_to_dev(psr->hw), psr->xlt_kb_sw);
+ devm_kfree(ice_hw_to_dev(psr->hw), psr->xlt_kb_acl);
+ devm_kfree(ice_hw_to_dev(psr->hw), psr->xlt_kb_fd);
+ devm_kfree(ice_hw_to_dev(psr->hw), psr->xlt_kb_rss);
devm_kfree(ice_hw_to_dev(psr->hw), psr);
}
diff --git a/drivers/net/ethernet/intel/ice/ice_parser.h b/drivers/net/ethernet/intel/ice/ice_parser.h
index 62123788e0a2..ca71ef4f50f5 100644
--- a/drivers/net/ethernet/intel/ice/ice_parser.h
+++ b/drivers/net/ethernet/intel/ice/ice_parser.h
@@ -12,6 +12,7 @@
#include "ice_mk_grp.h"
#include "ice_proto_grp.h"
#include "ice_flg_rd.h"
+#include "ice_xlt_kb.h"
#define ICE_SEC_DATA_OFFSET 4
#define ICE_SID_RXPARSER_IMEM_ENTRY_SIZE 48
@@ -56,6 +57,14 @@ struct ice_parser {
struct ice_proto_grp_item *proto_grp_table;
/* load data from section ICE_SID_RXPARSER_FLAG_REDIR */
struct ice_flg_rd_item *flg_rd_table;
+ /* load data from section ICE_SID_XLT_KEY_BUILDER_SW */
+ struct ice_xlt_kb *xlt_kb_sw;
+ /* load data from section ICE_SID_XLT_KEY_BUILDER_ACL */
+ struct ice_xlt_kb *xlt_kb_acl;
+ /* load data from section ICE_SID_XLT_KEY_BUILDER_FD */
+ struct ice_xlt_kb *xlt_kb_fd;
+ /* load data from section ICE_SID_XLT_KEY_BUILDER_RSS */
+ struct ice_xlt_kb *xlt_kb_rss;
};
int ice_parser_create(struct ice_hw *hw, struct ice_parser **psr);
diff --git a/drivers/net/ethernet/intel/ice/ice_xlt_kb.c b/drivers/net/ethernet/intel/ice/ice_xlt_kb.c
new file mode 100644
index 000000000000..4fca88fb7d77
--- /dev/null
+++ b/drivers/net/ethernet/intel/ice/ice_xlt_kb.c
@@ -0,0 +1,235 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright (C) 2023 Intel Corporation */
+
+#include "ice_common.h"
+
+static void _ice_xlt_kb_entry_dump(struct ice_hw *hw,
+ struct ice_xlt_kb_entry *entry, int idx)
+{
+ int i;
+
+ dev_info(ice_hw_to_dev(hw), "key builder entry %d\n", idx);
+ dev_info(ice_hw_to_dev(hw), "\txlt1_ad_sel = %d\n",
+ entry->xlt1_ad_sel);
+ dev_info(ice_hw_to_dev(hw), "\txlt2_ad_sel = %d\n",
+ entry->xlt2_ad_sel);
+
+ for (i = 0; i < ICE_XLT_KB_FLAG0_14_CNT; i++)
+ dev_info(ice_hw_to_dev(hw), "\tflg%d_sel = %d\n", i,
+ entry->flg0_14_sel[i]);
+
+ dev_info(ice_hw_to_dev(hw), "\txlt1_md_sel = %d\n",
+ entry->xlt1_md_sel);
+ dev_info(ice_hw_to_dev(hw), "\txlt2_md_sel = %d\n",
+ entry->xlt2_md_sel);
+}
+
+/**
+ * ice_xlt_kb_dump - dump a xlt key build info
+ * @hw: pointer to the hardware structure
+ * @kb: key build to dump
+ */
+void ice_xlt_kb_dump(struct ice_hw *hw, struct ice_xlt_kb *kb)
+{
+ int i;
+
+ dev_info(ice_hw_to_dev(hw), "xlt1_pm = %d\n", kb->xlt1_pm);
+ dev_info(ice_hw_to_dev(hw), "xlt2_pm = %d\n", kb->xlt2_pm);
+ dev_info(ice_hw_to_dev(hw), "prof_id_pm = %d\n", kb->prof_id_pm);
+ dev_info(ice_hw_to_dev(hw), "flag15 lo = 0x%08x\n", (u32)kb->flag15);
+ dev_info(ice_hw_to_dev(hw), "flag15 hi = 0x%08x\n",
+ (u32)(kb->flag15 >> (sizeof(u32) * BITS_PER_BYTE)));
+
+ for (i = 0; i < ICE_XLT_KB_TBL_CNT; i++)
+ _ice_xlt_kb_entry_dump(hw, &kb->entries[i], i);
+}
+
+/** The function parses a 192 bits XLT Key Builder entry with below format:
+ * BIT 0-31: reserved
+ * BIT 32-34: XLT1 AdSel (entry->xlt1_ad_sel)
+ * BIT 35-37: XLT2 AdSel (entry->xlt2_ad_sel)
+ * BIT 38-46: Flag 0 Select (entry->flg0_14_sel[0])
+ * BIT 47-55: Flag 1 Select (entry->flg0_14_sel[1])
+ * BIT 56-64: Flag 2 Select (entry->flg0_14_sel[2])
+ * BIT 65-73: Flag 3 Select (entry->flg0_14_sel[3])
+ * BIT 74-82: Flag 4 Select (entry->flg0_14_sel[4])
+ * BIT 83-91: Flag 5 Select (entry->flg0_14_sel[5])
+ * BIT 92-100: Flag 6 Select (entry->flg0_14_sel[6])
+ * BIT 101-109:Flag 7 Select (entry->flg0_14_sel[7])
+ * BIT 110-118:Flag 8 Select (entry->flg0_14_sel[8])
+ * BIT 119-127:Flag 9 Select (entry->flg0_14_sel[9])
+ * BIT 128-136:Flag 10 Select (entry->flg0_14_sel[10])
+ * BIT 137-145:Flag 11 Select (entry->flg0_14_sel[11])
+ * BIT 146-154:Flag 12 Select (entry->flg0_14_sel[12])
+ * BIT 155-163:Flag 13 Select (entry->flg0_14_sel[13])
+ * BIT 164-172:Flag 14 Select (entry->flg0_14_sel[14])
+ * BIT 173-181:reserved
+ * BIT 182-186:XLT1 MdSel (entry->xlt1_md_sel)
+ * BIT 187-191:XLT2 MdSel (entry->xlt2_md_sel)
+ */
+static void _ice_kb_entry_init(struct ice_xlt_kb_entry *entry, u8 *data)
+{
+ u8 idd, off, i;
+ u64 d64;
+
+ idd = ICE_XLT_KB_X1AS_S / BITS_PER_BYTE;
+ off = ICE_XLT_KB_X1AS_S % BITS_PER_BYTE;
+ d64 = *((u64 *)&data[idd]) >> off;
+
+ off = ICE_XLT_KB_X1AS_S - ICE_XLT_KB_X1AS_S;
+ entry->xlt1_ad_sel = (u8)((d64 >> off) & ICE_XLT_KB_X1AS_M);
+ off = ICE_XLT_KB_X2AS_S - ICE_XLT_KB_X1AS_S;
+ entry->xlt2_ad_sel = (u8)((d64 >> off) & ICE_XLT_KB_X2AS_M);
+
+ i = 0;
+ off = ICE_XLT_KB_FL00_S - ICE_XLT_KB_X1AS_S;
+ entry->flg0_14_sel[i] = (u16)((d64 >> off) & ICE_XLT_KB_FL00_M);
+ i++;
+ off = ICE_XLT_KB_FL01_S - ICE_XLT_KB_X1AS_S;
+ entry->flg0_14_sel[i] = (u16)((d64 >> off) & ICE_XLT_KB_FL01_M);
+ i++;
+ off = ICE_XLT_KB_FL02_S - ICE_XLT_KB_X1AS_S;
+ entry->flg0_14_sel[i] = (u16)((d64 >> off) & ICE_XLT_KB_FL02_M);
+ i++;
+ off = ICE_XLT_KB_FL03_S - ICE_XLT_KB_X1AS_S;
+ entry->flg0_14_sel[i] = (u16)((d64 >> off) & ICE_XLT_KB_FL03_M);
+ i++;
+ off = ICE_XLT_KB_FL04_S - ICE_XLT_KB_X1AS_S;
+ entry->flg0_14_sel[i] = (u16)((d64 >> off) & ICE_XLT_KB_FL04_M);
+ i++;
+ off = ICE_XLT_KB_FL05_S - ICE_XLT_KB_X1AS_S;
+ entry->flg0_14_sel[i] = (u16)((d64 >> off) & ICE_XLT_KB_FL05_M);
+
+ idd = ICE_XLT_KB_FL06_S / BITS_PER_BYTE;
+ off = ICE_XLT_KB_FL06_S % BITS_PER_BYTE;
+ d64 = *((u64 *)&data[idd]) >> off;
+
+ i++;
+ off = ICE_XLT_KB_FL06_S - ICE_XLT_KB_FL06_S;
+ entry->flg0_14_sel[i] = (u16)((d64 >> off) & ICE_XLT_KB_FL06_M);
+ i++;
+ off = ICE_XLT_KB_FL07_S - ICE_XLT_KB_FL06_S;
+ entry->flg0_14_sel[i] = (u16)((d64 >> off) & ICE_XLT_KB_FL07_M);
+ i++;
+ off = ICE_XLT_KB_FL08_S - ICE_XLT_KB_FL06_S;
+ entry->flg0_14_sel[i] = (u16)((d64 >> off) & ICE_XLT_KB_FL08_M);
+ i++;
+ off = ICE_XLT_KB_FL09_S - ICE_XLT_KB_FL06_S;
+ entry->flg0_14_sel[i] = (u16)((d64 >> off) & ICE_XLT_KB_FL09_M);
+ i++;
+ off = ICE_XLT_KB_FL10_S - ICE_XLT_KB_FL06_S;
+ entry->flg0_14_sel[i] = (u16)((d64 >> off) & ICE_XLT_KB_FL10_M);
+ i++;
+ off = ICE_XLT_KB_FL11_S - ICE_XLT_KB_FL06_S;
+ entry->flg0_14_sel[i] = (u16)((d64 >> off) & ICE_XLT_KB_FL11_M);
+
+ idd = ICE_XLT_KB_FL12_S / BITS_PER_BYTE;
+ off = ICE_XLT_KB_FL12_S % BITS_PER_BYTE;
+ d64 = *((u64 *)&data[idd]) >> off;
+
+ i++;
+ off = ICE_XLT_KB_FL12_S - ICE_XLT_KB_FL12_S;
+ entry->flg0_14_sel[i] = (u16)((d64 >> off) & ICE_XLT_KB_FL12_M);
+ i++;
+ off = ICE_XLT_KB_FL13_S - ICE_XLT_KB_FL12_S;
+ entry->flg0_14_sel[i] = (u16)((d64 >> off) & ICE_XLT_KB_FL13_M);
+ i++;
+ off = ICE_XLT_KB_FL14_S - ICE_XLT_KB_FL12_S;
+ entry->flg0_14_sel[i] = (u16)((d64 >> off) & ICE_XLT_KB_FL14_M);
+
+ off = ICE_XLT_KB_X1MS_S - ICE_XLT_KB_FL12_S;
+ entry->xlt1_md_sel = (u8)((d64 >> off) & ICE_XLT_KB_X1MS_M);
+ off = ICE_XLT_KB_X2MS_S - ICE_XLT_KB_FL12_S;
+ entry->xlt2_md_sel = (u8)((d64 >> off) & ICE_XLT_KB_X2MS_M);
+}
+
+/** The function parses a 204 bytes XLT Key Build Table with below format:
+ * byte 0: XLT1 Partition Mode (kb->xlt1_pm)
+ * byte 1: XLT2 Partition Mode (kb->xlt2_pm)
+ * byte 2: Profile ID Partition Mode (kb->prof_id_pm)
+ * byte 3: reserved
+ * byte 4-11: Flag15 Mask (kb->flag15)
+ * byte 12-203:8 Key Build entries (kb->entries)
+ */
+static void _ice_parse_kb_data(struct ice_hw *hw, struct ice_xlt_kb *kb,
+ void *data)
+{
+ u8 *buf = data;
+ int i;
+
+ kb->xlt1_pm = buf[ICE_XLT_KB_X1PM_OFF];
+ kb->xlt2_pm = buf[ICE_XLT_KB_X2PM_OFF];
+ kb->prof_id_pm = buf[ICE_XLT_KB_PIPM_OFF];
+
+ kb->flag15 = *(u64 *)&buf[ICE_XLT_KB_FL15_OFF];
+ for (i = 0; i < ICE_XLT_KB_TBL_CNT; i++)
+ _ice_kb_entry_init(&kb->entries[i],
+ &buf[ICE_XLT_KB_TBL_OFF +
+ i * ICE_XLT_KB_TBL_ENTRY_SIZE]);
+
+ if (hw->debug_mask & ICE_DBG_PARSER)
+ ice_xlt_kb_dump(hw, kb);
+}
+
+static struct ice_xlt_kb *_ice_xlt_kb_get(struct ice_hw *hw, u32 sect_type)
+{
+ struct ice_seg *seg = hw->seg;
+ struct ice_pkg_enum state;
+ struct ice_xlt_kb *kb;
+ void *data;
+
+ if (!seg)
+ return NULL;
+
+ kb = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*kb), GFP_KERNEL);
+ if (!kb)
+ return NULL;
+
+ memset(&state, 0, sizeof(state));
+ data = ice_pkg_enum_section(seg, &state, sect_type);
+ if (!data) {
+ ice_debug(hw, ICE_DBG_PARSER, "failed to find section type %d.\n",
+ sect_type);
+ return NULL;
+ }
+
+ _ice_parse_kb_data(hw, kb, data);
+
+ return kb;
+}
+
+/**
+ * ice_xlt_kb_get_sw - create switch xlt key build
+ * @hw: pointer to the hardware structure
+ */
+struct ice_xlt_kb *ice_xlt_kb_get_sw(struct ice_hw *hw)
+{
+ return _ice_xlt_kb_get(hw, ICE_SID_XLT_KEY_BUILDER_SW);
+}
+
+/**
+ * ice_xlt_kb_get_acl - create acl xlt key build
+ * @hw: pointer to the hardware structure
+ */
+struct ice_xlt_kb *ice_xlt_kb_get_acl(struct ice_hw *hw)
+{
+ return _ice_xlt_kb_get(hw, ICE_SID_XLT_KEY_BUILDER_ACL);
+}
+
+/**
+ * ice_xlt_kb_get_fd - create fdir xlt key build
+ * @hw: pointer to the hardware structure
+ */
+struct ice_xlt_kb *ice_xlt_kb_get_fd(struct ice_hw *hw)
+{
+ return _ice_xlt_kb_get(hw, ICE_SID_XLT_KEY_BUILDER_FD);
+}
+
+/**
+ * ice_xlt_kb_get_rss - create rss xlt key build
+ * @hw: pointer to the hardware structure
+ */
+struct ice_xlt_kb *ice_xlt_kb_get_rss(struct ice_hw *hw)
+{
+ return _ice_xlt_kb_get(hw, ICE_SID_XLT_KEY_BUILDER_RSS);
+}
diff --git a/drivers/net/ethernet/intel/ice/ice_xlt_kb.h b/drivers/net/ethernet/intel/ice/ice_xlt_kb.h
new file mode 100644
index 000000000000..020f96bfdbe8
--- /dev/null
+++ b/drivers/net/ethernet/intel/ice/ice_xlt_kb.h
@@ -0,0 +1,79 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright (C) 2023 Intel Corporation */
+
+#ifndef _ICE_XLT_KB_H_
+#define _ICE_XLT_KB_H_
+
+#define ICE_XLT_KB_FLAG0_14_CNT 15
+
+#define ICE_XLT_KB_FLAG_M BITMAP_MASK(9)
+#define ICE_XLT_KB_X1AS_S 32
+#define ICE_XLT_KB_X1AS_M BITMAP_MASK(3)
+#define ICE_XLT_KB_X2AS_S 35
+#define ICE_XLT_KB_X2AS_M BITMAP_MASK(3)
+#define ICE_XLT_KB_FL00_S 38
+#define ICE_XLT_KB_FL00_M BITMAP_MASK(9)
+#define ICE_XLT_KB_FL01_S 47
+#define ICE_XLT_KB_FL01_M BITMAP_MASK(9)
+#define ICE_XLT_KB_FL02_S 56
+#define ICE_XLT_KB_FL02_M BITMAP_MASK(9)
+#define ICE_XLT_KB_FL03_S 65
+#define ICE_XLT_KB_FL03_M BITMAP_MASK(9)
+#define ICE_XLT_KB_FL04_S 74
+#define ICE_XLT_KB_FL04_M BITMAP_MASK(9)
+#define ICE_XLT_KB_FL05_S 83
+#define ICE_XLT_KB_FL05_M BITMAP_MASK(9)
+#define ICE_XLT_KB_FL06_S 92
+#define ICE_XLT_KB_FL06_M BITMAP_MASK(9)
+#define ICE_XLT_KB_FL07_S 101
+#define ICE_XLT_KB_FL07_M BITMAP_MASK(9)
+#define ICE_XLT_KB_FL08_S 110
+#define ICE_XLT_KB_FL08_M BITMAP_MASK(9)
+#define ICE_XLT_KB_FL09_S 119
+#define ICE_XLT_KB_FL09_M BITMAP_MASK(9)
+#define ICE_XLT_KB_FL10_S 128
+#define ICE_XLT_KB_FL10_M BITMAP_MASK(9)
+#define ICE_XLT_KB_FL11_S 137
+#define ICE_XLT_KB_FL11_M BITMAP_MASK(9)
+#define ICE_XLT_KB_FL12_S 146
+#define ICE_XLT_KB_FL12_M BITMAP_MASK(9)
+#define ICE_XLT_KB_FL13_S 155
+#define ICE_XLT_KB_FL13_M BITMAP_MASK(9)
+#define ICE_XLT_KB_FL14_S 164
+#define ICE_XLT_KB_FL14_M BITMAP_MASK(9)
+#define ICE_XLT_KB_X1MS_S 182
+#define ICE_XLT_KB_X1MS_M BITMAP_MASK(5)
+#define ICE_XLT_KB_X2MS_S 187
+#define ICE_XLT_KB_X2MS_M BITMAP_MASK(5)
+
+struct ice_xlt_kb_entry {
+ u8 xlt1_ad_sel;
+ u8 xlt2_ad_sel;
+ u16 flg0_14_sel[ICE_XLT_KB_FLAG0_14_CNT];
+ u8 xlt1_md_sel;
+ u8 xlt2_md_sel;
+};
+
+#define ICE_XLT_KB_X1PM_OFF 0
+#define ICE_XLT_KB_X2PM_OFF 1
+#define ICE_XLT_KB_PIPM_OFF 2
+#define ICE_XLT_KB_FL15_OFF 4
+#define ICE_XLT_KB_TBL_CNT 8
+#define ICE_XLT_KB_TBL_OFF 12
+#define ICE_XLT_KB_TBL_ENTRY_SIZE 24
+
+struct ice_xlt_kb {
+ u8 xlt1_pm;
+ u8 xlt2_pm;
+ u8 prof_id_pm;
+ u64 flag15;
+
+ struct ice_xlt_kb_entry entries[ICE_XLT_KB_TBL_CNT];
+};
+
+void ice_xlt_kb_dump(struct ice_hw *hw, struct ice_xlt_kb *kb);
+struct ice_xlt_kb *ice_xlt_kb_get_sw(struct ice_hw *hw);
+struct ice_xlt_kb *ice_xlt_kb_get_acl(struct ice_hw *hw);
+struct ice_xlt_kb *ice_xlt_kb_get_fd(struct ice_hw *hw);
+struct ice_xlt_kb *ice_xlt_kb_get_rss(struct ice_hw *hw);
+#endif /* _ICE_XLT_KB_H */
--
2.25.1
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