netdev - Re: [PATCH net-next v7 1/6] page_pool: frag API support for 32-bit arch with 64-bit DMA

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Message-ID: <2b570282-24f8-f23b-1ff7-ad836794baa9@huawei.com>
Date: Tue, 29 Aug 2023 19:58:32 +0800
From: Yunsheng Lin <linyunsheng@...wei.com>
To: Jakub Kicinski <kuba@...nel.org>, Alexander Duyck
	<alexander.duyck@...il.com>
CC: Ilias Apalodimas <ilias.apalodimas@...aro.org>, Mina Almasry
	<almasrymina@...gle.com>, <davem@...emloft.net>, <pabeni@...hat.com>,
	<netdev@...r.kernel.org>, <linux-kernel@...r.kernel.org>, Lorenzo Bianconi
	<lorenzo@...nel.org>, Liang Chen <liangchen.linux@...il.com>, Alexander
 Lobakin <aleksander.lobakin@...el.com>, Saeed Mahameed <saeedm@...dia.com>,
	Leon Romanovsky <leon@...nel.org>, Eric Dumazet <edumazet@...gle.com>, Jesper
 Dangaard Brouer <hawk@...nel.org>
Subject: Re: [PATCH net-next v7 1/6] page_pool: frag API support for 32-bit
 arch with 64-bit DMA

On 2023/8/28 23:38, Jakub Kicinski wrote:
> On Mon, 28 Aug 2023 07:50:33 -0700 Alexander Duyck wrote:
>> Actually we could keep it pretty simple. We just have to create a
>> #define using DMA_BIT_MASK for the size of the page pool DMA. We could
>> name it something like PP_DMA_BIT_MASK. The drivers would just have to
>> use that to define their bit mask when they call
>> dma_set_mask_and_coherent. In that case the DMA API would switch to
>> bounce buffers automatically in cases where the page DMA address would
>> be out of bounds.
>>
>> The other tweak we could look at doing would be to just look at the
>> dma_get_required_mask and add a warning and/or fail to load page pool
>> on systems where the page pool would not be able to process that when
>> ANDed with the device dma mask.

As the all arches have used CONFIG_PHYS_ADDR_T_64BIT:
https://elixir.free-electrons.com/linux/v6.4-rc6/K/ident/CONFIG_PHYS_ADDR_T_64BIT

arm: Large Physical Address Extension or LPAE, 40 bits of phys addr.
arc: Physical Address Extension or PAE, 40 bits of phys addr.
mips: eXtended Physical Addressing or PXA, 40 bits of phys addr.
powerpc: does not seems to have a name for the feature, and have 36
         bits of phys addr.
riscv: large physical address, 34 bits of phys addr.
x86: Physical Address Extension or PAE, 36 bits of phys addr.

It do seem that we are worrying too much, So I am going to follow jakub's
suggestion. If we make a wrong assumption, we print a warning for that.

>>
>> With those two changes the setup should be rock solid in terms of any
>> risks of the DMA address being out of bounds, and with minimal
>> performance impact as we would have verified all possibilities before
>> we even get into the hot path.
> 
> Sounds like a plan!
> .
>