netdev - RE: [PATCH v3 1/3] dt-bindings: can: xilinx_can: Add ECC property 'xlnx,has-ecc'

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite for Android: free password hash cracker in your pocket

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID:
 <PH8PR12MB6675C31C6D1DCD3281FE8A10E1E6A@PH8PR12MB6675.namprd12.prod.outlook.com>
Date: Wed, 30 Aug 2023 06:06:18 +0000
From: "Goud, Srinivas" <srinivas.goud@....com>
To: Rob Herring <robh@...nel.org>
CC: "wg@...ndegger.com" <wg@...ndegger.com>, "mkl@...gutronix.de"
	<mkl@...gutronix.de>, "davem@...emloft.net" <davem@...emloft.net>,
	"edumazet@...gle.com" <edumazet@...gle.com>, "kuba@...nel.org"
	<kuba@...nel.org>, "pabeni@...hat.com" <pabeni@...hat.com>,
	"krzysztof.kozlowski+dt@...aro.org" <krzysztof.kozlowski+dt@...aro.org>,
	"conor+dt@...nel.org" <conor+dt@...nel.org>, "p.zabel@...gutronix.de"
	<p.zabel@...gutronix.de>, "git (AMD-Xilinx)" <git@....com>, "Simek, Michal"
	<michal.simek@....com>, "linux-can@...r.kernel.org"
	<linux-can@...r.kernel.org>, "linux-arm-kernel@...ts.infradead.org"
	<linux-arm-kernel@...ts.infradead.org>, "linux-kernel@...r.kernel.org"
	<linux-kernel@...r.kernel.org>, "netdev@...r.kernel.org"
	<netdev@...r.kernel.org>, "devicetree@...r.kernel.org"
	<devicetree@...r.kernel.org>, "appana.durga.rao@...inx.com"
	<appana.durga.rao@...inx.com>, "naga.sureshkumar.relli@...inx.com"
	<naga.sureshkumar.relli@...inx.com>
Subject: RE: [PATCH v3 1/3] dt-bindings: can: xilinx_can: Add ECC property
 'xlnx,has-ecc'

Hi Rob,

>-----Original Message-----
>From: Rob Herring <robh@...nel.org>
>Sent: Monday, August 28, 2023 9:13 PM
>To: Goud, Srinivas <srinivas.goud@....com>
>Cc: wg@...ndegger.com; mkl@...gutronix.de; davem@...emloft.net;
>edumazet@...gle.com; kuba@...nel.org; pabeni@...hat.com;
>krzysztof.kozlowski+dt@...aro.org; conor+dt@...nel.org;
>p.zabel@...gutronix.de; git (AMD-Xilinx) <git@....com>; Simek, Michal
><michal.simek@....com>; linux-can@...r.kernel.org; linux-arm-
>kernel@...ts.infradead.org; linux-kernel@...r.kernel.org;
>netdev@...r.kernel.org; devicetree@...r.kernel.org;
>appana.durga.rao@...inx.com; naga.sureshkumar.relli@...inx.com
>Subject: Re: [PATCH v3 1/3] dt-bindings: can: xilinx_can: Add ECC property
>'xlnx,has-ecc'
>
>On Mon, Aug 28, 2023 at 08:28:43PM +0530, Srinivas Goud wrote:
>> ECC feature added to Tx and Rx FIFOs for Xilinx AXI CAN Controller.
>> Part of this feature configuration and counter registers added in IP
>> for 1bit/2bit ECC errors.
>>
>> xlnx,has-ecc is optional property and added to Xilinx AXI CAN
>> Controller node if ECC block enabled in the HW
>>
>> Signed-off-by: Srinivas Goud <srinivas.goud@....com>
>> ---
>> Changes in v3:
>> Update commit description
>>
>> Changes in v2:
>> None
>
>Doesn't apply, dependency?
This patch is created on top of below commit and this is part of the 
linux-can-next/master and Linux torvalds GIT
https://lore.kernel.org/all/bfaed896cc51af02fe5f290675313ab4dcab0d33.1689164442.git.michal.simek@amd.com/

>
>>
>>  Documentation/devicetree/bindings/net/can/xilinx,can.yaml | 5 +++++
>>  1 file changed, 5 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/net/can/xilinx,can.yaml
>> b/Documentation/devicetree/bindings/net/can/xilinx,can.yaml
>> index 64d57c3..c842610 100644
>> --- a/Documentation/devicetree/bindings/net/can/xilinx,can.yaml
>> +++ b/Documentation/devicetree/bindings/net/can/xilinx,can.yaml
>> @@ -49,6 +49,10 @@ properties:
>>    resets:
>>      maxItems: 1
>>
>> +  xlnx,has-ecc:
>> +    $ref: /schemas/types.yaml#/definitions/flag
>> +    description: CAN Tx and Rx fifo ECC enable flag (AXI CAN)
>
>has ECC or enable ECC?
Will update description with "has ECC"

>
>> +
>>  required:
>>    - compatible
>>    - reg
>> @@ -137,6 +141,7 @@ examples:
>>          interrupts = <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>;
>>          tx-fifo-depth = <0x40>;
>>          rx-fifo-depth = <0x40>;
>> +        xlnx,has-ecc
>
>Obviously not tested.
Will fix it.

Thanks,
Srinivas