netdev - Re: [PATCH net-next v2 1/2] dt-bindings: net: Add documentation for Half duplex support.

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Message-ID: <90b3e6cc-7246-4d02-bd0f-2ce7847bc261@lunn.ch>
Date: Tue, 12 Sep 2023 17:16:44 +0200
From: Andrew Lunn <andrew@...n.ch>
To: MD Danish Anwar <danishanwar@...com>
Cc: Rob Herring <robh@...nel.org>, Roger Quadros <rogerq@...com>,
	Conor Dooley <conor+dt@...nel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
	Paolo Abeni <pabeni@...hat.com>, Jakub Kicinski <kuba@...nel.org>,
	Eric Dumazet <edumazet@...gle.com>,
	"David S. Miller" <davem@...emloft.net>,
	Vignesh Raghavendra <vigneshr@...com>,
	Simon Horman <horms@...nel.org>, linux-kernel@...r.kernel.org,
	devicetree@...r.kernel.org, netdev@...r.kernel.org, srk@...com,
	r-gunasekaran@...com, Roger Quadros <rogerq@...nel.org>
Subject: Re: [PATCH net-next v2 1/2] dt-bindings: net: Add documentation for
 Half duplex support.

> Sure Rob, I will change the description to below.
> 
>     description:
>       Indicates that the PHY output pin (COL) is routed to ICSSG GPIO

The PHY has multiple output pins, so i would not put COL in brackets,
but make it explicit which pin you are referring to.

>       pin (PRGx_PRU0/1_GPIO10) as input and ICSSG MII port is capable
>       of half duplex operations.

"input and so the ICSSG MII port is"

       Andrew