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Date: Wed, 13 Sep 2023 15:42:45 +0100
From: Conor Dooley <conor@...nel.org>
To: Herve Codina <herve.codina@...tlin.com>
Cc: "David S. Miller" <davem@...emloft.net>,
	Eric Dumazet <edumazet@...gle.com>,
	Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>,
	Andrew Lunn <andrew@...n.ch>, Rob Herring <robh+dt@...nel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
	Conor Dooley <conor+dt@...nel.org>, Lee Jones <lee@...nel.org>,
	Linus Walleij <linus.walleij@...aro.org>,
	Qiang Zhao <qiang.zhao@....com>, Li Yang <leoyang.li@....com>,
	Liam Girdwood <lgirdwood@...il.com>,
	Mark Brown <broonie@...nel.org>, Jaroslav Kysela <perex@...ex.cz>,
	Takashi Iwai <tiwai@...e.com>,
	Shengjiu Wang <shengjiu.wang@...il.com>,
	Xiubo Li <Xiubo.Lee@...il.com>, Fabio Estevam <festevam@...il.com>,
	Nicolin Chen <nicoleotsuka@...il.com>,
	Christophe Leroy <christophe.leroy@...roup.eu>,
	Randy Dunlap <rdunlap@...radead.org>, netdev@...r.kernel.org,
	linuxppc-dev@...ts.ozlabs.org, devicetree@...r.kernel.org,
	linux-kernel@...r.kernel.org, linux-gpio@...r.kernel.org,
	linux-arm-kernel@...ts.infradead.org, alsa-devel@...a-project.org,
	Simon Horman <horms@...nel.org>,
	Christophe JAILLET <christophe.jaillet@...adoo.fr>,
	Thomas Petazzoni <thomas.petazzoni@...tlin.com>
Subject: Re: [PATCH v5 08/31] dt-bindings: soc: fsl: cpm_qe: cpm1-scc-qmc:
 Add support for QMC HDLC

On Wed, Sep 13, 2023 at 09:26:40AM +0200, Herve Codina wrote:
> Hi Conor,
> 
> On Tue, 12 Sep 2023 18:21:58 +0100
> Conor Dooley <conor@...nel.org> wrote:
> 
> > On Tue, Sep 12, 2023 at 12:10:18PM +0200, Herve Codina wrote:
> > > The QMC (QUICC mutichannel controller) is a controller present in some
> > > PowerQUICC SoC such as MPC885.
> > > The QMC HDLC uses the QMC controller to transfer HDLC data.
> > > 
> > > Additionally, a framer can be connected to the QMC HDLC.
> > > If present, this framer is the interface between the TDM bus used by the
> > > QMC HDLC and the E1/T1 line.
> > > The QMC HDLC can use this framer to get information about the E1/T1 line
> > > and configure the E1/T1 line.
> > > 
> > > Signed-off-by: Herve Codina <herve.codina@...tlin.com>
> > > ---
> > >  .../bindings/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml   | 13 +++++++++++++
> > >  1 file changed, 13 insertions(+)
> > > 
> > > diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml
> > > index 82d9beb48e00..b5073531f3f1 100644
> > > --- a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml
> > > +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml
> > > @@ -101,6 +101,16 @@ patternProperties:
> > >            Channel assigned Rx time-slots within the Rx time-slots routed by the
> > >            TSA to this cell.
> > >  
> > > +      compatible:
> > > +        const: fsl,qmc-hdlc
> > > +
> > > +      fsl,framer:
> > > +        $ref: /schemas/types.yaml#/definitions/phandle
> > > +        description:
> > > +          phandle to the framer node. The framer is in charge of an E1/T1 line
> > > +          interface connected to the TDM bus. It can be used to get the E1/T1 line
> > > +          status such as link up/down.  
> > 
> > Sounds like this fsl,framer property should depend on the compatible
> > being present, no?
> 
> Well from the implementation point of view, only the QMC HDLC driver uses this
> property.
> 
> From the hardware description point of view, this property means that the time slots
> handled by this channel are connected to the framer. So I think it makes sense for
> any channel no matter the compatible (even if compatible is not present).
> 
> Should I change and constraint the fsl,framer property to the compatible presence ?
> If so, is the following correct for this contraint ?
>    --- 8< ---
>    dependencies:
>      - fsl,framer: [ compatible ];
>    --- 8< ---

The regular sort of
if:
	compatible:
		contains:
			const: foo
then:
	required:
		- fsl,framer
would fit the bill, no?

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