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Message-ID: <20230914103526.GX401982@kernel.org> Date: Thu, 14 Sep 2023 12:35:26 +0200 From: Simon Horman <horms@...nel.org> To: MD Danish Anwar <danishanwar@...com> Cc: Andrew Lunn <andrew@...n.ch>, Roger Quadros <rogerq@...com>, Conor Dooley <conor+dt@...nel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>, Rob Herring <robh+dt@...nel.org>, Paolo Abeni <pabeni@...hat.com>, Jakub Kicinski <kuba@...nel.org>, Eric Dumazet <edumazet@...gle.com>, "David S. Miller" <davem@...emloft.net>, Vignesh Raghavendra <vigneshr@...com>, linux-kernel@...r.kernel.org, devicetree@...r.kernel.org, netdev@...r.kernel.org, srk@...com, r-gunasekaran@...com, Roger Quadros <rogerq@...nel.org> Subject: Re: [PATCH net-next v2 1/2] dt-bindings: net: Add documentation for Half duplex support. On Mon, Sep 11, 2023 at 11:31:59AM +0530, MD Danish Anwar wrote: > In order to support half-duplex operation at 10M and 100M link speeds, the > PHY collision detection signal (COL) should be routed to ICSSG > GPIO pin (PRGx_PRU0/1_GPI10) so that firmware can detect collision signal > and apply the CSMA/CD algorithm applicable for half duplex operation. A DT > property, "ti,half-duplex-capable" is introduced for this purpose. If > board has PHY COL pin conencted to PRGx_PRU1_GPIO10, this DT property can nit: connected ...
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