netdev - Re: [RFC PATCH net-next 5/6] microchip: lan865x: add driver support for Microchip's LAN865X MACPHY

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Date: Mon, 18 Sep 2023 11:22:11 +0000
From: <Parthiban.Veerasooran@...rochip.com>
To: <david.wretman@...roamp.se>
CC: <Nicolas.Ferre@...rochip.com>, <Thorsten.Kummermehr@...rochip.com>,
	<UNGLinuxDriver@...rochip.com>, <Woojung.Huh@...rochip.com>,
	<andrew@...n.ch>, <casper.casan@...il.com>, <conor+dt@...nel.org>,
	<corbet@....net>, <davem@...emloft.net>, <devicetree@...r.kernel.org>,
	<edumazet@...gle.com>, <Horatiu.Vultur@...rochip.com>, <horms@...nel.org>,
	<krzysztof.kozlowski+dt@...aro.org>, <kuba@...nel.org>,
	<linux-doc@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
	<netdev@...r.kernel.org>, <pabeni@...hat.com>, <rdunlap@...radead.org>,
	<robh+dt@...nel.org>, <Steen.Hegelund@...rochip.com>
Subject: Re: [RFC PATCH net-next 5/6] microchip: lan865x: add driver support
 for Microchip's LAN865X MACPHY

Hi David,

Thanks for your comments. Please see my reply below,

On 15/09/23 6:31 pm, David Wretman wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> ---
> On Fri, Sep 08, 2023 at 07:59:18PM +0530, Parthiban Veerasooran wrote:
>> The LAN8650/1 is designed to conform to the OPEN Alliance 10BASE‑T1x
>> MAC‑PHY Serial Interface specification, Version 1.1. The IEEE Clause 4
>> MAC integration provides the low pin count standard SPI interface to any
>> microcontroller therefore providing Ethernet functionality without
>> requiring MAC integration within the microcontroller. The LAN8650/1
>> operates as an SPI client supporting SCLK clock rates up to a maximum of
>> 25 MHz. This SPI interface supports the transfer of both data (Ethernet
>> frames) and control (register access).
>>
>> By default, the chunk data payload is 64 bytes in size. A smaller payload
>> data size of 32 bytes is also supported and may be configured in the
>> Chunk Payload Size (CPS) field of the Configuration 0 (OA_CONFIG0)
>> register. Changing the chunk payload size requires the LAN8650/1 be reset
>> and shall not be done during normal operation.
>>
>> The Ethernet Media Access Controller (MAC) module implements a 10 Mbps
>> half duplex Ethernet MAC, compatible with the IEEE 802.3 standard.
>> 10BASE-T1S physical layer transceiver integrated into the LAN8650/1. The
>> PHY and MAC are connected via an internal Media Independent Interface
>> (MII).
>>
>> Signed-off-by: Parthiban Veerasooran <Parthiban.Veerasooran@...rochip.com>
> 
> Hi Parthiban,
> 
> Thanks for these patches.
> 
> One thing I am missing is settings for PLCA parameters. I feel that the
> driver is a bit lacking as long as this is missing.
No it is not missed. The driver still supports for setting the PLCA 
parameters using ethtool. This is just a MAC driver and its internal 
PHY's driver is already mainlined which has PLCA setting support. Please 
have a look in the below link which has the implementation.

https://elixir.bootlin.com/linux/latest/source/drivers/net/phy/microchip_t1s.c#L283

You can use the below ethtool command to set your PLCA settings.

$ ethtool --set-plca-cfg eth1 enable on node-id 0 node-cnt 8 to-tmr 0x20 
burst-cnt 0x0 burst-tmr 0x80
> 
> Adding support for the ethtool plca options would make this much more
> complete.
Hope the above explanation helps. Please let me know if I misunderstand 
your comment.

Best Regards,
Parthiban V
> 
> Regards,
> David
>