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Date: Sat, 23 Sep 2023 16:49:04 +0300
From: Vladimir Oltean <vladimir.oltean@....com>
To: netdev@...r.kernel.org,
devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org,
linux-phy@...ts.infradead.org
Cc: "Russell King (Oracle)" <rmk+kernel@...linux.org.uk>,
Heiner Kallweit <hkallweit1@...il.com>,
Andrew Lunn <andrew@...n.ch>,
Florian Fainelli <f.fainelli@...il.com>,
Madalin Bucur <madalin.bucur@....com>,
Ioana Ciornei <ioana.ciornei@....com>,
Camelia Groza <camelia.groza@....com>,
Li Yang <leoyang.li@....com>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor@...nel.org>,
Sean Anderson <sean.anderson@...o.com>,
Maxime Chevallier <maxime.chevallier@...tlin.com>,
Vinod Koul <vkoul@...nel.org>,
Kishon Vijay Abraham I <kishon@...nel.org>
Subject: [RFC PATCH v2 net-next 15/15] net: pcs: lynx: use MTIP AN/LT block for copper backplanes
If the fsl,backplane-mode device tree property is present, then the Lynx
PCS makes use of the AN/LT block to advertise the supported backplane
link modes using clause 73 autoneg.
Signed-off-by: Vladimir Oltean <vladimir.oltean@....com>
---
v1->v2: code is new
drivers/net/pcs/Kconfig | 1 +
drivers/net/pcs/pcs-lynx.c | 135 +++++++++++++++++++++++++++++++++++++
2 files changed, 136 insertions(+)
diff --git a/drivers/net/pcs/Kconfig b/drivers/net/pcs/Kconfig
index 24a033e93bdd..be561c465b4a 100644
--- a/drivers/net/pcs/Kconfig
+++ b/drivers/net/pcs/Kconfig
@@ -13,6 +13,7 @@ config MTIP_BACKPLANE_PHY
SoCs.
config PCS_XPCS
+ depends on MTIP_BACKPLANE_PHY || MTIP_BACKPLANE_PHY=n
tristate
select PHYLINK
help
diff --git a/drivers/net/pcs/pcs-lynx.c b/drivers/net/pcs/pcs-lynx.c
index dc3962b2aa6b..1352f08edcf3 100644
--- a/drivers/net/pcs/pcs-lynx.c
+++ b/drivers/net/pcs/pcs-lynx.c
@@ -4,10 +4,14 @@
*/
#include <linux/mdio.h>
+#include <linux/of.h>
+#include <linux/phy/phy.h>
#include <linux/phylink.h>
#include <linux/pcs-lynx.h>
#include <linux/property.h>
+#include "mtip_backplane.h"
+
#define SGMII_CLOCK_PERIOD_NS 8 /* PCS is clocked at 125 MHz */
#define LINK_TIMER_VAL(ns) ((u32)((ns) / SGMII_CLOCK_PERIOD_NS))
@@ -20,9 +24,15 @@
#define IF_MODE_SPEED_MSK GENMASK(3, 2)
#define IF_MODE_HALF_DUPLEX BIT(4)
+#define PRIMARY_LANE 0
+#define MAX_NUM_LANES 4
+
struct lynx_pcs {
struct phylink_pcs pcs;
struct mdio_device *mdio;
+ struct mtip_backplane *anlt[MAX_NUM_LANES];
+ int num_lanes;
+ bool backplane_mode;
};
enum sgmii_speed {
@@ -100,6 +110,9 @@ static void lynx_pcs_get_state(struct phylink_pcs *pcs,
case PHY_INTERFACE_MODE_10GBASER:
phylink_mii_c45_pcs_get_state(lynx->mdio, state);
break;
+ case PHY_INTERFACE_MODE_INTERNAL:
+ mtip_backplane_get_state(lynx->anlt[PRIMARY_LANE], state);
+ break;
default:
break;
}
@@ -168,6 +181,17 @@ static int lynx_pcs_config_usxgmii(struct mdio_device *pcs,
ADVERTISE_SGMII | ADVERTISE_LPACK);
}
+static int lynx_pcs_config_backplane(struct phylink_pcs *pcs,
+ unsigned int neg_mode,
+ const unsigned long *advertising)
+{
+ bool autoneg = neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED;
+ struct lynx_pcs *lynx = phylink_pcs_to_lynx(pcs);
+
+ return mtip_backplane_config_aneg(lynx->anlt[PRIMARY_LANE], autoneg,
+ advertising);
+}
+
static int lynx_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode,
phy_interface_t ifmode,
const unsigned long *advertising, bool permit)
@@ -193,6 +217,8 @@ static int lynx_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode,
case PHY_INTERFACE_MODE_10GBASER:
/* Nothing to do here for 10GBASER */
break;
+ case PHY_INTERFACE_MODE_INTERNAL:
+ return lynx_pcs_config_backplane(pcs, neg_mode, advertising);
default:
return -EOPNOTSUPP;
}
@@ -204,6 +230,9 @@ static void lynx_pcs_an_restart(struct phylink_pcs *pcs)
{
struct lynx_pcs *lynx = phylink_pcs_to_lynx(pcs);
+ if (lynx->backplane_mode)
+ return mtip_backplane_an_restart(lynx->anlt[PRIMARY_LANE]);
+
phylink_mii_c22_pcs_an_restart(lynx->mdio);
}
@@ -306,16 +335,111 @@ static void lynx_pcs_link_up(struct phylink_pcs *pcs, unsigned int neg_mode,
}
}
+static int lynx_pcs_validate(struct phylink_pcs *pcs, unsigned long *supported,
+ const struct phylink_link_state *state)
+{
+ struct lynx_pcs *lynx = phylink_pcs_to_lynx(pcs);
+
+ if (state->interface != PHY_INTERFACE_MODE_INTERNAL)
+ return 0;
+
+ return mtip_backplane_validate(lynx->anlt[PRIMARY_LANE], supported);
+}
+
+static int lynx_pcs_enable(struct phylink_pcs *pcs)
+{
+ struct lynx_pcs *lynx = phylink_pcs_to_lynx(pcs);
+ int err;
+
+ if (lynx->backplane_mode) {
+ err = mtip_backplane_resume(lynx->anlt[PRIMARY_LANE]);
+ if (err)
+ return err;
+ }
+
+ return 0;
+}
+
+static void lynx_pcs_disable(struct phylink_pcs *pcs)
+{
+ struct lynx_pcs *lynx = phylink_pcs_to_lynx(pcs);
+
+ if (lynx->backplane_mode)
+ mtip_backplane_suspend(lynx->anlt[PRIMARY_LANE]);
+}
+
static const struct phylink_pcs_ops lynx_pcs_phylink_ops = {
.pcs_get_state = lynx_pcs_get_state,
.pcs_config = lynx_pcs_config,
.pcs_an_restart = lynx_pcs_an_restart,
.pcs_link_up = lynx_pcs_link_up,
+ .pcs_validate = lynx_pcs_validate,
+ .pcs_enable = lynx_pcs_enable,
+ .pcs_disable = lynx_pcs_disable,
};
+static int lynx_pcs_parse_fwnode(struct lynx_pcs *lynx)
+{
+ struct fwnode_handle *node = lynx->mdio->dev.fwnode;
+ enum mtip_model model = MTIP_MODEL_AUTODETECT;
+ struct device_node *np = to_of_node(node);
+ struct mdio_device *mdio = lynx->mdio;
+ struct device *dev = &mdio->dev;
+ struct phy *phy;
+ int i, err;
+
+ if (!node)
+ return 0;
+
+ lynx->backplane_mode = fwnode_property_present(node, "fsl,backplane-mode");
+ if (!lynx->backplane_mode)
+ return 0;
+
+ if (fwnode_device_is_compatible(node, "fsl,lx2160a-lynx-pcs"))
+ model = MTIP_MODEL_LX2160A;
+
+ lynx->num_lanes = of_count_phandle_with_args(np, "phys", "#phy-cells");
+ if (lynx->num_lanes < 0)
+ return lynx->num_lanes;
+
+ if (WARN_ON(lynx->num_lanes > MAX_NUM_LANES))
+ return -EINVAL;
+
+ for (i = 0; i < lynx->num_lanes; i++) {
+ phy = devm_of_phy_get_by_index(dev, np, i);
+ if (IS_ERR(phy))
+ return dev_err_probe(dev, PTR_ERR(phy),
+ "Failed to get SerDes PHY %d\n", i);
+
+ lynx->anlt[i] = mtip_backplane_create(mdio, phy, model);
+ if (IS_ERR(lynx->anlt[i])) {
+ err = PTR_ERR(lynx->anlt[i]);
+
+ while (i-- > 0)
+ mtip_backplane_destroy(lynx->anlt[i]);
+
+ return err;
+ }
+ }
+
+ for (i = 1; i < lynx->num_lanes; i++) {
+ err = mtip_backplane_add_subordinate(lynx->anlt[PRIMARY_LANE],
+ lynx->anlt[i]);
+ if (WARN_ON(err)) {
+ /* Too many SerDes lanes in the device tree? */
+ for (i = 0; i < lynx->num_lanes; i++)
+ mtip_backplane_destroy(lynx->anlt[i]);
+ return err;
+ }
+ }
+
+ return 0;
+}
+
static struct phylink_pcs *lynx_pcs_create(struct mdio_device *mdio)
{
struct lynx_pcs *lynx;
+ int err;
lynx = kzalloc(sizeof(*lynx), GFP_KERNEL);
if (!lynx)
@@ -327,6 +451,12 @@ static struct phylink_pcs *lynx_pcs_create(struct mdio_device *mdio)
lynx->pcs.neg_mode = true;
lynx->pcs.poll = true;
+ err = lynx_pcs_parse_fwnode(lynx);
+ if (err) {
+ kfree(lynx);
+ return ERR_PTR(err);
+ }
+
return lynx_to_phylink_pcs(lynx);
}
@@ -392,6 +522,11 @@ EXPORT_SYMBOL_GPL(lynx_pcs_create_fwnode);
void lynx_pcs_destroy(struct phylink_pcs *pcs)
{
struct lynx_pcs *lynx = phylink_pcs_to_lynx(pcs);
+ int i;
+
+ if (lynx->backplane_mode)
+ for (i = 0; i < lynx->num_lanes; i++)
+ mtip_backplane_destroy(lynx->anlt[i]);
mdio_device_put(lynx->mdio);
kfree(lynx);
--
2.34.1
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