netdev - Re: [PATCH net] net: ethernet: renesas: rswitch Fix PHY station management clock setting

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Message-ID: <7156d89e-ef72-487f-b7ce-b08be461ec1c@lunn.ch>
Date: Mon, 25 Sep 2023 16:17:49 +0200
From: Andrew Lunn <andrew@...n.ch>
To: Yoshihiro Shimoda <yoshihiro.shimoda.uh@...esas.com>
Cc: s.shtylyov@....ru, davem@...emloft.net, edumazet@...gle.com,
	kuba@...nel.org, pabeni@...hat.com, netdev@...r.kernel.org,
	linux-renesas-soc@...r.kernel.org,
	Tam Nguyen <tam.nguyen.xa@...esas.com>,
	Kuninori Morimoto <kuninori.morimoto.gx@...esas.com>
Subject: Re: [PATCH net] net: ethernet: renesas: rswitch Fix PHY station
 management clock setting

On Mon, Sep 25, 2023 at 09:34:16AM +0900, Yoshihiro Shimoda wrote:
> From: Tam Nguyen <tam.nguyen.xa@...esas.com>
> 
> Fix the MPIC.PSMCS value following the programming example in the
> section 6.4.2 Management Data Clock (MDC) Setting, Ethernet MAC IP,
> S4 Hardware User Manual Rev.1.00.
> 
> The value is calculated by
>     MPIC.PSMCS = clk[MHz] / ((MDC frequency[MHz] + 1) * 2)
> with the input clock frequency of 320MHz and MDC frequency of 2.5MHz.
> Otherwise, this driver cannot communicate PHYs on the R-Car S4 Starter
> Kit board.

If you run this calculation backwards, what frequency does
MPIC_PSMCS(0x3f) map to?

Is 320MHz really fixed? For all silicon variants? Is it possible to do
a clk_get_rate() on a clock to get the actual clock rate?

	Andrew