netdev - RE: [PATCH net] net: ethernet: renesas: rswitch Fix PHY station management clock setting

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Message-ID:
 <TYBPR01MB53419F7AFFF80FAB49C4F92BD8C2A@TYBPR01MB5341.jpnprd01.prod.outlook.com>
Date: Wed, 27 Sep 2023 00:35:23 +0000
From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@...esas.com>
To: Andrew Lunn <andrew@...n.ch>
CC: "s.shtylyov@....ru" <s.shtylyov@....ru>, "davem@...emloft.net"
	<davem@...emloft.net>, "edumazet@...gle.com" <edumazet@...gle.com>,
	"kuba@...nel.org" <kuba@...nel.org>, "pabeni@...hat.com" <pabeni@...hat.com>,
	"netdev@...r.kernel.org" <netdev@...r.kernel.org>,
	"linux-renesas-soc@...r.kernel.org" <linux-renesas-soc@...r.kernel.org>, Tam
 Nguyen <tam.nguyen.xa@...esas.com>, Kuninori Morimoto
	<kuninori.morimoto.gx@...esas.com>
Subject: RE: [PATCH net] net: ethernet: renesas: rswitch Fix PHY station
 management clock setting

Hello Andrew,

> From: Andrew Lunn, Sent: Tuesday, September 26, 2023 9:48 PM
> 
> On Tue, Sep 26, 2023 at 07:21:59AM +0000, Yoshihiro Shimoda wrote:
> > Hello Andrew,
> >
> > > From: Andrew Lunn, Sent: Monday, September 25, 2023 11:18 PM
> > >
> > > On Mon, Sep 25, 2023 at 09:34:16AM +0900, Yoshihiro Shimoda wrote:
> > > > From: Tam Nguyen <tam.nguyen.xa@...esas.com>
> > > >
> > > > Fix the MPIC.PSMCS value following the programming example in the
> > > > section 6.4.2 Management Data Clock (MDC) Setting, Ethernet MAC IP,
> > > > S4 Hardware User Manual Rev.1.00.
> > > >
> > > > The value is calculated by
> > > >     MPIC.PSMCS = clk[MHz] / ((MDC frequency[MHz] + 1) * 2)
> > > > with the input clock frequency of 320MHz and MDC frequency of 2.5MHz.
> > > > Otherwise, this driver cannot communicate PHYs on the R-Car S4 Starter
> > > > Kit board.
> > >
> > > If you run this calculation backwards, what frequency does
> > > MPIC_PSMCS(0x3f) map to?
> >
> > Thank you for your review! I completely misunderstood the formula. In
> > other words, the formula cannot calculate backwards. The correct
> > formula is:
> >
> > MPIC.PSMCS = clk[MHz] / (MDC frequency[MHz] * 2) - 1
> >
> > > Is 320MHz really fixed? For all silicon variants? Is it possible to do
> > > a clk_get_rate() on a clock to get the actual clock rate?
> >
> > 320MHz is really fixed on the current existing all silicon variants.
> > Yes, it is possible to do a clk_get_rate() on a clock to get the actual
> > clock rate. So, I'll use clk_get_rate() on v2.
> 
> Was the original version tested?

Yes, the original version was tested on Spider board.
The original version's MDC frequency was 25MHz.
And the PHY (Marvell 88E2110) on Spider board can use such frequency,
IIUC because the MDC period is 35 ns (so 28.57143MHz).

However, I don't know why this setting cannot work on the Starter Kit board
because the board also has the same PHY. I guess that this is related to
board design, especially voltage of I/O (Spider = 1.8V, Starter Kit = 3.3V).

Anyway, changing the MDC frequency from 25MHz to 2.5MHz works correctly on
both Spider and Starter Kit. So, I would like to apply the v3 patch [1] for safe.

[1] https://lore.kernel.org/all/20230926123054.3976752-1-yoshihiro.shimoda.uh@renesas.com/

> I've run Marvell PHYs are 5Mhz, sometimes 6MHz. This is within spec as
> given by the datasheet, even if IEEE 802.3 says 2.5Mhz is the max.
> 
> Now if MPIC_PSMCS(0x3f) maps to 20MHz or more, it could never of
> worked, which makes me think the clock has changed. If it maps to
> 6Mhz, yes it could of worked with some PHY but not others, and the
> clock might not of changed.

I'm sorry for lacking information. MPIC_PSMCS(0x3f) maps to 2.5MHz.

Best regards,
Yoshihiro Shimoda

>       Andrew