--- drivers/net/ethernet/stmicro/stmmac/dwmac5_est.c 2023-10-03 13:08:04.149201098 +0300 +++ drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core_est.c 2023-10-03 13:11:30.034936292 +0300 @@ -1,186 +1,187 @@ -#define MTL_EST_CONTROL 0x00000c50 -#define PTOV GENMASK(31, 24) -#define PTOV_SHIFT 24 -#define SSWL BIT(1) -#define EEST BIT(0) - -#define MTL_EST_STATUS 0x00000c58 -#define BTRL GENMASK(11, 8) -#define BTRL_SHIFT 8 -#define BTRL_MAX (0xF << BTRL_SHIFT) -#define SWOL BIT(7) -#define SWOL_SHIFT 7 -#define CGCE BIT(4) -#define HLBS BIT(3) -#define HLBF BIT(2) -#define BTRE BIT(1) -#define SWLC BIT(0) - -#define MTL_EST_SCH_ERR 0x00000c60 -#define MTL_EST_FRM_SZ_ERR 0x00000c64 -#define MTL_EST_FRM_SZ_CAP 0x00000c68 -#define SZ_CAP_HBFS_MASK GENMASK(14, 0) -#define SZ_CAP_HBFQ_SHIFT 16 -#define SZ_CAP_HBFQ_MASK(_val) \ +#define XGMAC_MTL_EST_CONTROL 0x00001050 +#define XGMAC_PTOV GENMASK(31, 23) +#define XGMAC_PTOV_SHIFT 23 +#define XGMAC_SSWL BIT(1) +#define XGMAC_EEST BIT(0) + +#define XGMAC_MTL_EST_STATUS 0x00001058 +#define XGMAC_BTRL GENMASK(15, 8) +#define XGMAC_BTRL_SHIFT 8 +#define XGMAC_BTRL_MAX GENMASK(15, 8) +#define XGMAC_CGCE BIT(4) +#define XGMAC_HLBS BIT(3) +#define XGMAC_HLBF BIT(2) +#define XGMAC_BTRE BIT(1) +#define XGMAC_SWLC BIT(0) + +#define XGMAC_MTL_EST_SCH_ERR 0x00001060 +#define XGMAC_MTL_EST_FRM_SZ_ERR 0x00001064 +#define XGMAC_MTL_EST_FRM_SZ_CAP 0x00001068 +#define XGMAC_SZ_CAP_HBFS_MASK GENMASK(14, 0) +#define XGMAC_SZ_CAP_HBFQ_SHIFT 16 +#define XGMAC_SZ_CAP_HBFQ_MASK(val) \ ({ \ - typeof(_val) (val) = (_val); \ - ((val) > 4 ? GENMASK(18, 16) : \ - (val) > 2 ? GENMASK(17, 16) : \ + typeof(val) _val = (val); \ + (_val > 4 ? GENMASK(18, 16) : \ + _val > 2 ? GENMASK(17, 16) : \ BIT(16)); \ }) -#define MTL_EST_INT_EN 0x00000c70 -#define IECGCE CGCE -#define IEHS HLBS -#define IEHF HLBF -#define IEBE BTRE -#define IECC SWLC - -#define MTL_EST_GCL_CONTROL 0x00000c80 -#define BTR_LOW 0x0 -#define BTR_HIGH 0x1 -#define CTR_LOW 0x2 -#define CTR_HIGH 0x3 -#define TER 0x4 -#define LLR 0x5 -#define ADDR_SHIFT 8 -#define GCRR BIT(2) -#define SRWO BIT(0) -#define MTL_EST_GCL_DATA 0x00000c84 +#define XGMAC_MTL_EST_INT_EN 0x00001070 +#define XGMAC_IECGCE BIT(4) +#define XGMAC_IEHS BIT(3) +#define XGMAC_IEHF BIT(2) +#define XGMAC_IEBE BIT(1) +#define XGMAC_IECC BIT(0) + +#define XGMAC_MTL_EST_GCL_CONTROL 0x00001080 +#define XGMAC_BTR_LOW 0x0 +#define XGMAC_BTR_HIGH 0x1 +#define XGMAC_CTR_LOW 0x2 +#define XGMAC_CTR_HIGH 0x3 +#define XGMAC_TER 0x4 +#define XGMAC_LLR 0x5 +#define XGMAC_ADDR_SHIFT 8 +#define XGMAC_GCRR BIT(2) +#define XGMAC_SRWO BIT(0) +#define XGMAC_MTL_EST_GCL_DATA 0x00001084 -static int dwmac5_est_write(void __iomem *ioaddr, u32 reg, u32 val, bool gcl) +static int dwxgmac3_est_write(void __iomem *ioaddr, u32 reg, u32 val, bool gcl) { u32 ctrl; - writel(val, ioaddr + MTL_EST_GCL_DATA); + writel(val, ioaddr + XGMAC_MTL_EST_GCL_DATA); - ctrl = (reg << ADDR_SHIFT); - ctrl |= gcl ? 0 : GCRR; + ctrl = (reg << XGMAC_ADDR_SHIFT); + ctrl |= gcl ? 0 : XGMAC_GCRR; - writel(ctrl, ioaddr + MTL_EST_GCL_CONTROL); + writel(ctrl, ioaddr + XGMAC_MTL_EST_GCL_CONTROL); - ctrl |= SRWO; - writel(ctrl, ioaddr + MTL_EST_GCL_CONTROL); + ctrl |= XGMAC_SRWO; + writel(ctrl, ioaddr + XGMAC_MTL_EST_GCL_CONTROL); - return readl_poll_timeout(ioaddr + MTL_EST_GCL_CONTROL, - ctrl, !(ctrl & SRWO), 100, 5000); + return readl_poll_timeout_atomic(ioaddr + XGMAC_MTL_EST_GCL_CONTROL, + ctrl, !(ctrl & XGMAC_SRWO), 100, 5000); } -int dwmac5_est_configure(void __iomem *ioaddr, struct stmmac_est *cfg, - unsigned int ptp_rate) +static int dwxgmac3_est_configure(void __iomem *ioaddr, struct stmmac_est *cfg, + unsigned int ptp_rate) { int i, ret = 0x0; u32 ctrl; - ret |= dwmac5_est_write(ioaddr, BTR_LOW, cfg->btr[0], false); - ret |= dwmac5_est_write(ioaddr, BTR_HIGH, cfg->btr[1], false); - ret |= dwmac5_est_write(ioaddr, TER, cfg->ter, false); - ret |= dwmac5_est_write(ioaddr, LLR, cfg->gcl_size, false); - ret |= dwmac5_est_write(ioaddr, CTR_LOW, cfg->ctr[0], false); - ret |= dwmac5_est_write(ioaddr, CTR_HIGH, cfg->ctr[1], false); + ret |= dwxgmac3_est_write(ioaddr, XGMAC_BTR_LOW, cfg->btr[0], false); + ret |= dwxgmac3_est_write(ioaddr, XGMAC_BTR_HIGH, cfg->btr[1], false); + ret |= dwxgmac3_est_write(ioaddr, XGMAC_TER, cfg->ter, false); + ret |= dwxgmac3_est_write(ioaddr, XGMAC_LLR, cfg->gcl_size, false); + ret |= dwxgmac3_est_write(ioaddr, XGMAC_CTR_LOW, cfg->ctr[0], false); + ret |= dwxgmac3_est_write(ioaddr, XGMAC_CTR_HIGH, cfg->ctr[1], false); if (ret) return ret; for (i = 0; i < cfg->gcl_size; i++) { - ret = dwmac5_est_write(ioaddr, i, cfg->gcl[i], true); + ret = dwxgmac3_est_write(ioaddr, i, cfg->gcl[i], true); if (ret) return ret; } - ctrl = readl(ioaddr + MTL_EST_CONTROL); - ctrl &= ~PTOV; - ctrl |= ((1000000000 / ptp_rate) * 6) << PTOV_SHIFT; + ctrl = readl(ioaddr + XGMAC_MTL_EST_CONTROL); + ctrl &= ~XGMAC_PTOV; + ctrl |= ((1000000000 / ptp_rate) * 9) << XGMAC_PTOV_SHIFT; if (cfg->enable) - ctrl |= EEST | SSWL; + ctrl |= XGMAC_EEST | XGMAC_SSWL; else - ctrl &= ~EEST; + ctrl &= ~XGMAC_EEST; - writel(ctrl, ioaddr + MTL_EST_CONTROL); + writel(ctrl, ioaddr + XGMAC_MTL_EST_CONTROL); /* Configure EST interrupt */ if (cfg->enable) - ctrl = (IECGCE | IEHS | IEHF | IEBE | IECC); + ctrl = XGMAC_IECGCE | XGMAC_IEHS | XGMAC_IEHF | XGMAC_IEBE | + XGMAC_IECC; else ctrl = 0; - writel(ctrl, ioaddr + MTL_EST_INT_EN); + writel(ctrl, ioaddr + XGMAC_MTL_EST_INT_EN); return 0; } -void dwmac5_est_irq_status(void __iomem *ioaddr, struct net_device *dev, - struct stmmac_extra_stats *x, u32 txqcnt) +static void dwxgmac3_est_irq_status(void __iomem *ioaddr, + struct net_device *dev, + struct stmmac_extra_stats *x, u32 txqcnt) { u32 status, value, feqn, hbfq, hbfs, btrl; - u32 txqcnt_mask = (1 << txqcnt) - 1; + u32 txqcnt_mask = BIT(txqcnt) - 1; - status = readl(ioaddr + MTL_EST_STATUS); + status = readl(ioaddr + XGMAC_MTL_EST_STATUS); - value = (CGCE | HLBS | HLBF | BTRE | SWLC); + value = XGMAC_CGCE | XGMAC_HLBS | XGMAC_HLBF | XGMAC_BTRE | XGMAC_SWLC; /* Return if there is no error */ if (!(status & value)) return; - if (status & CGCE) { + if (status & XGMAC_CGCE) { /* Clear Interrupt */ - writel(CGCE, ioaddr + MTL_EST_STATUS); + writel(XGMAC_CGCE, ioaddr + XGMAC_MTL_EST_STATUS); x->mtl_est_cgce++; } - if (status & HLBS) { - value = readl(ioaddr + MTL_EST_SCH_ERR); + if (status & XGMAC_HLBS) { + value = readl(ioaddr + XGMAC_MTL_EST_SCH_ERR); value &= txqcnt_mask; x->mtl_est_hlbs++; /* Clear Interrupt */ - writel(value, ioaddr + MTL_EST_SCH_ERR); + writel(value, ioaddr + XGMAC_MTL_EST_SCH_ERR); /* Collecting info to shows all the queues that has HLBS * issue. The only way to clear this is to clear the - * statistic + * statistic. */ if (net_ratelimit()) netdev_err(dev, "EST: HLB(sched) Queue 0x%x\n", value); } - if (status & HLBF) { - value = readl(ioaddr + MTL_EST_FRM_SZ_ERR); + if (status & XGMAC_HLBF) { + value = readl(ioaddr + XGMAC_MTL_EST_FRM_SZ_ERR); feqn = value & txqcnt_mask; - value = readl(ioaddr + MTL_EST_FRM_SZ_CAP); - hbfq = (value & SZ_CAP_HBFQ_MASK(txqcnt)) >> SZ_CAP_HBFQ_SHIFT; - hbfs = value & SZ_CAP_HBFS_MASK; + value = readl(ioaddr + XGMAC_MTL_EST_FRM_SZ_CAP); + hbfq = (value & XGMAC_SZ_CAP_HBFQ_MASK(txqcnt)) >> + XGMAC_SZ_CAP_HBFQ_SHIFT; + hbfs = value & XGMAC_SZ_CAP_HBFS_MASK; x->mtl_est_hlbf++; /* Clear Interrupt */ - writel(feqn, ioaddr + MTL_EST_FRM_SZ_ERR); + writel(feqn, ioaddr + XGMAC_MTL_EST_FRM_SZ_ERR); if (net_ratelimit()) netdev_err(dev, "EST: HLB(size) Queue %u Size %u\n", hbfq, hbfs); } - if (status & BTRE) { - if ((status & BTRL) == BTRL_MAX) + if (status & XGMAC_BTRE) { + if ((status & XGMAC_BTRL) == XGMAC_BTRL_MAX) x->mtl_est_btrlm++; else x->mtl_est_btre++; - btrl = (status & BTRL) >> BTRL_SHIFT; + btrl = (status & XGMAC_BTRL) >> XGMAC_BTRL_SHIFT; if (net_ratelimit()) netdev_info(dev, "EST: BTR Error Loop Count %u\n", btrl); - writel(BTRE, ioaddr + MTL_EST_STATUS); + writel(XGMAC_BTRE, ioaddr + XGMAC_MTL_EST_STATUS); } - if (status & SWLC) { - writel(SWLC, ioaddr + MTL_EST_STATUS); + if (status & XGMAC_SWLC) { + writel(XGMAC_SWLC, ioaddr + XGMAC_MTL_EST_STATUS); netdev_info(dev, "EST: SWOL has been switched\n"); } }