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Message-ID: <643c55ca-4eca-4dfc-9176-cf46c2504057@gmail.com>
Date: Wed, 4 Oct 2023 13:00:04 -0700
From: Florian Fainelli <f.fainelli@...il.com>
To: Shenwei Wang <shenwei.wang@....com>, "David S. Miller"
<davem@...emloft.net>, Eric Dumazet <edumazet@...gle.com>,
Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>,
Shawn Guo <shawnguo@...nel.org>, Sascha Hauer <s.hauer@...gutronix.de>,
Maxime Coquelin <mcoquelin.stm32@...il.com>
Cc: Alexandre Torgue <alexandre.torgue@...s.st.com>,
Jose Abreu <joabreu@...opsys.com>,
Pengutronix Kernel Team <kernel@...gutronix.de>,
Fabio Estevam <festevam@...il.com>, NXP Linux Team <linux-imx@....com>,
netdev@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-stm32@...md-mailman.stormreply.com, imx@...ts.linux.dev,
Mario Castaneda <mario.ignacio.castaneda.lopez@....com>
Subject: Re: [PATCH net] net: stmmac: dwmac-imx: request high frequency mode
On 10/4/23 12:54, Shenwei Wang wrote:
> Some i.MX SoCs like the i.mx8mq support adjusting the frequency of the
> DDR, AHB, and AXI buses based on system loading. If the dwmac interface
> in the driver does not request a HIGH frequency, it can significantly
> degrade performance when the system switches to a lower frequency to
> conserve power.
>
> For example, on an i.MX8MQ EVK board, the throughput dropped to around
> 100Mbit/s on a 1Gbit connection:
>
> [ ID] Interval Transfer Bitrate
> [ 5] 0.00-10.00 sec 117 MBytes 97.9 Mbits/sec
>
> However, throughput can return to expected levels after its driver requests
> the high frequency mode. Requesting high frequency in the dwmac driver is
> essential to maintain full throughput when the i.MX SoC adjusts bus speeds
> for power savings.
>
> Signed-off-by: Mario Castaneda <mario.ignacio.castaneda.lopez@....com>
> Signed-off-by: Shenwei Wang <shenwei.wang@....com>
> Tested-by: Mario Castaneda <mario.ignacio.castaneda.lopez@....com>
I assume that you cannot go full dynamic and adjust the bus frequency
based upon the negotiated link speed? There may be a need to adjust the
bus frequency prior to starting any DMA transfers, otherwise dynamic
frequency scaling of the bus may cause all sorts of issues?
Regardless of the answer:
Reviewed-by: Florian Fainelli <florian.fainelli@...adcom.com>
--
Florian
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