netdev - Re: [PATCH bpf 0/2] riscv, bpf: Properly sign-extend return values

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Date: Mon, 09 Oct 2023 13:30:25 +0000
From: patchwork-bot+netdevbpf@...nel.org
To: Björn Töpel <bjorn@...nel.org>@codeaurora.org
Cc: ast@...nel.org, daniel@...earbox.net, andrii@...nel.org,
 bpf@...r.kernel.org, netdev@...r.kernel.org, pulehui@...wei.com,
 bjorn@...osinc.com, linux-kernel@...r.kernel.org, luke.r.nels@...il.com,
 xi.wang@...il.com, linux-riscv@...ts.infradead.org
Subject: Re: [PATCH bpf 0/2] riscv, bpf: Properly sign-extend return values

Hello:

This series was applied to bpf/bpf.git (master)
by Daniel Borkmann <daniel@...earbox.net>:

On Wed,  4 Oct 2023 14:07:04 +0200 you wrote:
> From: Björn Töpel <bjorn@...osinc.com>
> 
> The RISC-V architecture does not expose sub-registers, and hold all
> 32-bit values in a sign-extended format [1] [2]:
> 
>   | The compiler and calling convention maintain an invariant that all
>   | 32-bit values are held in a sign-extended format in 64-bit
>   | registers. Even 32-bit unsigned integers extend bit 31 into bits
>   | 63 through 32. Consequently, conversion between unsigned and
>   | signed 32-bit integers is a no-op, as is conversion from a signed
>   | 32-bit integer to a signed 64-bit integer.
> 
> [...]

Here is the summary with links:
  - [bpf,1/2] riscv, bpf: Sign-extend return values
    https://git.kernel.org/bpf/bpf/c/2f1b0d3d7331
  - [bpf,2/2] riscv, bpf: Track both a0 (RISC-V ABI) and a5 (BPF) return values
    https://git.kernel.org/bpf/bpf/c/7112cd26e606

You are awesome, thank you!
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