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Message-ID: <CA+sq2CcA_Cv8sQ8_vqCAW=EoXTkCfoEE8QNWEQmnyHTNfK0wdA@mail.gmail.com> Date: Tue, 17 Oct 2023 16:56:42 +0530 From: Sunil Kovvuri <sunil.kovvuri@...il.com> To: Coco Li <lixiaoyan@...gle.com> Cc: Jakub Kicinski <kuba@...nel.org>, Eric Dumazet <edumazet@...gle.com>, Neal Cardwell <ncardwell@...gle.com>, Mubashir Adnan Qureshi <mubashirq@...gle.com>, Paolo Abeni <pabeni@...hat.com>, netdev@...r.kernel.org, Chao Wu <wwchao@...gle.com>, Wei Wang <weiwan@...gle.com> Subject: Re: [PATCH v1 net-next 0/5] Analyze and Reorganize core Networking Structs to optimize cacheline consumption > On AMD platforms with 100Gb/s NIC and 256Mb L3 cache: > IPv6 > Flows with patches clean kernel Percent reduction > 30k 0.000202535503 0.0003275329163 -38.16% > > On Intel platforms with 200Gb/s NIC and 105Mb L3 cache: > IPv6 > Flows with patches clean kernel Percent reduction > 30k 0.0006296537873 0.0006370427753 -1.16% > Great work !!. What are the L1/L2 cache size and cache line width on these AMD and Intel platforms ? Thanks, Sunil.
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