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Message-ID: <20231017124608.GA4386@lst.de> Date: Tue, 17 Oct 2023 14:46:08 +0200 From: Christoph Hellwig <hch@....de> To: Geert Uytterhoeven <geert@...ux-m68k.org> Cc: Christoph Hellwig <hch@....de>, Conor Dooley <conor.dooley@...rochip.com>, Greg Ungerer <gerg@...ux-m68k.org>, iommu@...ts.linux.dev, Paul Walmsley <paul.walmsley@...ive.com>, Palmer Dabbelt <palmer@...belt.com>, Conor Dooley <conor@...nel.org>, Magnus Damm <magnus.damm@...il.com>, Robin Murphy <robin.murphy@....com>, Marek Szyprowski <m.szyprowski@...sung.com>, Wei Fang <wei.fang@....com>, Shenwei Wang <shenwei.wang@....com>, Clark Wang <xiaoning.wang@....com>, NXP Linux Team <linux-imx@....com>, linux-m68k@...ts.linux-m68k.org, netdev@...r.kernel.org, linux-riscv@...ts.infradead.org, linux-renesas-soc@...r.kernel.org, Jim Quinlan <james.quinlan@...adcom.com>, arm-soc <soc@...nel.org> Subject: Re: [PATCH 04/12] soc: renesas: select RISCV_DMA_NONCOHERENT from ARCH_R9A07G043 On Tue, Oct 17, 2023 at 12:44:41PM +0200, Geert Uytterhoeven wrote: > Hi Christoph, > > On Mon, Oct 16, 2023 at 3:17 PM Christoph Hellwig <hch@....de> wrote: > > On Mon, Oct 16, 2023 at 01:52:57PM +0100, Conor Dooley wrote: > > > > + select RISCV_DMA_NONCOHERENT > > > > select ERRATA_ANDES if RISCV_SBI > > > > select ERRATA_ANDES_CMO if ERRATA_ANDES > > > > > > Since this Kconfig menu has changed a bit in linux-next, the selects > > > are unconditional here, and ERRATA_ANDES_CMO will in turn select > > > RISCV_DMA_NONCOHERENT. > > > > Oh, looks like another patch landed there in linux-next. I had > > waited for the previous one go go upstream in -rc6. Not sure > > how to best handle this conflict. > > I think the easiest is to ask soc to apply this series? I don't think pulling all the DMA bits into a random other tree would be a good idea. I can hand off the first few bits, but I'd need a stable branch to pull in after that. Which of the half a dozen soc trees we have in linux-next is this anyway?
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