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Message-ID: <3d4b86a5-6a92-4456-a270-9091bdf8157e@lunn.ch> Date: Tue, 24 Oct 2023 03:21:44 +0200 From: Andrew Lunn <andrew@...n.ch> To: Parthiban Veerasooran <Parthiban.Veerasooran@...rochip.com> Cc: davem@...emloft.net, edumazet@...gle.com, kuba@...nel.org, pabeni@...hat.com, robh+dt@...nel.org, krzysztof.kozlowski+dt@...aro.org, conor+dt@...nel.org, corbet@....net, steen.hegelund@...rochip.com, rdunlap@...radead.org, horms@...nel.org, casper.casan@...il.com, netdev@...r.kernel.org, devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, linux-doc@...r.kernel.org, horatiu.vultur@...rochip.com, Woojung.Huh@...rochip.com, Nicolas.Ferre@...rochip.com, UNGLinuxDriver@...rochip.com, Thorsten.Kummermehr@...rochip.com Subject: Re: [PATCH net-next v2 6/9] dt-bindings: net: oa-tc6: add PHY register access capability On Mon, Oct 23, 2023 at 09:16:46PM +0530, Parthiban Veerasooran wrote: > Direct PHY Register Access Capability indicates if PHY registers are > directly accessible within the SPI register memory space. Indirect PHY > Register Access Capability indicates if PHY registers are indirectly > accessible through the MDIO/MDC registers MDIOACCn. > > Signed-off-by: Parthiban Veerasooran <Parthiban.Veerasooran@...rochip.com> It is more normal to put all the bindings into one patch. Again, this seems like configuration, not a description of the hardware. Its also not clear to my why you would want to configure it. Andrew
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