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Message-ID: <20231029042712.520010-7-cristian.ciocaltea@collabora.com> Date: Sun, 29 Oct 2023 06:27:06 +0200 From: Cristian Ciocaltea <cristian.ciocaltea@...labora.com> To: "David S. Miller" <davem@...emloft.net>, Eric Dumazet <edumazet@...gle.com>, Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>, Rob Herring <robh+dt@...nel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>, Conor Dooley <conor+dt@...nel.org>, Emil Renner Berthing <kernel@...il.dk>, Samin Guo <samin.guo@...rfivetech.com>, Paul Walmsley <paul.walmsley@...ive.com>, Palmer Dabbelt <palmer@...belt.com>, Albert Ou <aou@...s.berkeley.edu>, Alexandre Torgue <alexandre.torgue@...s.st.com>, Jose Abreu <joabreu@...opsys.com>, Maxime Coquelin <mcoquelin.stm32@...il.com>, Richard Cochran <richardcochran@...il.com>, Giuseppe Cavallaro <peppe.cavallaro@...com> Cc: netdev@...r.kernel.org, devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, linux-riscv@...ts.infradead.org, linux-stm32@...md-mailman.stormreply.com, linux-arm-kernel@...ts.infradead.org, kernel@...labora.com Subject: [PATCH v2 06/12] riscv: dts: starfive: jh7100: Add dma-noncoherent property The RISC-V architecture is by default coherent, since it selects ARCH_DMA_DEFAULT_COHERENT, but the StarFive JH7100 is not, hence provide the dma-noncoherent property to the soc DT node. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@...labora.com> --- arch/riscv/boot/dts/starfive/jh7100.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi index e68cafe7545f..06bb157ce111 100644 --- a/arch/riscv/boot/dts/starfive/jh7100.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi @@ -144,6 +144,7 @@ soc { interrupt-parent = <&plic>; #address-cells = <2>; #size-cells = <2>; + dma-noncoherent; ranges; clint: clint@...0000 { -- 2.42.0
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