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Message-ID: <20231030-ipq5332-nsscc-v1-4-6162a2c65f0a@quicinc.com> Date: Mon, 30 Oct 2023 15:17:19 +0530 From: Kathiravan Thirumoorthy <quic_kathirav@...cinc.com> To: Bjorn Andersson <andersson@...nel.org>, Andy Gross <agross@...nel.org>, Konrad Dybcio <konrad.dybcio@...aro.org>, Michael Turquette <mturquette@...libre.com>, Stephen Boyd <sboyd@...nel.org>, Rob Herring <robh+dt@...nel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>, Conor Dooley <conor+dt@...nel.org>, Richard Cochran <richardcochran@...il.com>, Catalin Marinas <catalin.marinas@....com>, Will Deacon <will@...nel.org> CC: <linux-arm-msm@...r.kernel.org>, <linux-clk@...r.kernel.org>, <linux-kernel@...r.kernel.org>, <devicetree@...r.kernel.org>, <netdev@...r.kernel.org>, <linux-arm-kernel@...ts.infradead.org>, "Kathiravan Thirumoorthy" <quic_kathirav@...cinc.com> Subject: [PATCH 4/8] clk: qcom: ipq5332: add gpll0_out_aux clock Add support for gpll0_out_aux clock which acts as the parent for certain networking subsystem (NSS) clocks. Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@...cinc.com> --- drivers/clk/qcom/gcc-ipq5332.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/clk/qcom/gcc-ipq5332.c b/drivers/clk/qcom/gcc-ipq5332.c index 235849876a9a..966bb7ca8854 100644 --- a/drivers/clk/qcom/gcc-ipq5332.c +++ b/drivers/clk/qcom/gcc-ipq5332.c @@ -87,6 +87,19 @@ static struct clk_alpha_pll_postdiv gpll0 = { }, }; +static struct clk_alpha_pll_postdiv gpll0_out_aux = { + .offset = 0x20000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER_PLUS], + .width = 4, + .clkr.hw.init = &(struct clk_init_data) { + .name = "gpll0_out_aux", + .parent_hws = (const struct clk_hw *[]) { + &gpll0_main.clkr.hw }, + .num_parents = 1, + .ops = &clk_alpha_pll_postdiv_ro_ops, + }, +}; + static struct clk_alpha_pll gpll2_main = { .offset = 0x21000, .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER_PLUS], @@ -3393,6 +3406,7 @@ static struct clk_regmap *gcc_ipq5332_clocks[] = { [GCC_PCIE3X1_0_PIPE_CLK_SRC] = &gcc_pcie3x1_0_pipe_clk_src.clkr, [GCC_PCIE3X1_1_PIPE_CLK_SRC] = &gcc_pcie3x1_1_pipe_clk_src.clkr, [GCC_USB0_PIPE_CLK_SRC] = &gcc_usb0_pipe_clk_src.clkr, + [GPLL0_OUT_AUX] = &gpll0_out_aux.clkr, }; static const struct qcom_reset_map gcc_ipq5332_resets[] = { -- 2.34.1
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