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Message-ID: <CAJM55Z_2hdsvw8gdYLs2kZbRrH6xcM6+xCZn8BCf5zsWYyhY3w@mail.gmail.com> Date: Tue, 31 Oct 2023 07:40:56 -0700 From: Emil Renner Berthing <emil.renner.berthing@...onical.com> To: Cristian Ciocaltea <cristian.ciocaltea@...labora.com>, "David S. Miller" <davem@...emloft.net>, Eric Dumazet <edumazet@...gle.com>, Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>, Rob Herring <robh+dt@...nel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>, Conor Dooley <conor+dt@...nel.org>, Emil Renner Berthing <kernel@...il.dk>, Samin Guo <samin.guo@...rfivetech.com>, Paul Walmsley <paul.walmsley@...ive.com>, Palmer Dabbelt <palmer@...belt.com>, Albert Ou <aou@...s.berkeley.edu>, Alexandre Torgue <alexandre.torgue@...s.st.com>, Jose Abreu <joabreu@...opsys.com>, Maxime Coquelin <mcoquelin.stm32@...il.com>, Richard Cochran <richardcochran@...il.com>, Giuseppe Cavallaro <peppe.cavallaro@...com> Cc: netdev@...r.kernel.org, devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, linux-riscv@...ts.infradead.org, linux-stm32@...md-mailman.stormreply.com, linux-arm-kernel@...ts.infradead.org, kernel@...labora.com, Emil Renner Berthing <emil.renner.berthing@...onical.com> Subject: Re: [PATCH v2 08/12] riscv: dts: starfive: Add pool for coherent DMA memory on JH7100 boards Cristian Ciocaltea wrote: > From: Emil Renner Berthing <emil.renner.berthing@...onical.com> > > The StarFive JH7100 SoC has non-coherent device DMAs, but most drivers > expect to be able to allocate coherent memory for DMA descriptors and > such. However on the JH7100 DDR memory appears twice in the physical > memory map, once cached and once uncached: > > 0x00_8000_0000 - 0x08_7fff_ffff : Off chip DDR memory, cached > 0x10_0000_0000 - 0x17_ffff_ffff : Off chip DDR memory, uncached > > To use this uncached region we create a global DMA memory pool there and > reserve the corresponding area in the cached region. > > However the uncached region is fully above the 32bit address limit, so add > a dma-ranges map so the DMA address used for peripherals is still in the > regular cached region below the limit. Adding these nodes to the device tree won't actually do anything without enabling CONFIG_DMA_GLOBAL_POOL as is done here: https://github.com/esmil/linux/commit/e14ad9ff67fd51dcc76415d4cc7f3a30ffcba379 > > Link: https://github.com/starfive-tech/JH7100_Docs/blob/main/JH7100%20Data%20Sheet%20V01.01.04-EN%20(4-21-2021).pdf > Signed-off-by: Emil Renner Berthing <emil.renner.berthing@...onical.com> > Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@...labora.com> > --- > .../boot/dts/starfive/jh7100-common.dtsi | 24 +++++++++++++++++++ > 1 file changed, 24 insertions(+) > > diff --git a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi > index b93ce351a90f..504c73f01f14 100644 > --- a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi > +++ b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi > @@ -39,6 +39,30 @@ led-ack { > label = "ack"; > }; > }; > + > + reserved-memory { > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + dma-reserved { > + reg = <0x0 0xfa000000 0x0 0x1000000>; > + no-map; > + }; > + > + linux,dma { > + compatible = "shared-dma-pool"; > + reg = <0x10 0x7a000000 0x0 0x1000000>; > + no-map; > + linux,dma-default; > + }; > + }; > + > + soc { > + dma-ranges = <0x00 0x80000000 0x00 0x80000000 0x00 0x7a000000>, > + <0x00 0xfa000000 0x10 0x7a000000 0x00 0x01000000>, > + <0x00 0xfb000000 0x00 0xfb000000 0x07 0x85000000>; > + }; > }; > > &gpio { > -- > 2.42.0 >
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