netdev - Re: [PATCH] net: phy: at803x: add QCA8084 ethernet phy support

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Date: Sun, 5 Nov 2023 16:09:08 +0800
From: Jie Luo <quic_luoj@...cinc.com>
To: "Russell King (Oracle)" <linux@...linux.org.uk>
CC: <andrew@...n.ch>, <hkallweit1@...il.com>, <davem@...emloft.net>,
        <edumazet@...gle.com>, <kuba@...nel.org>, <pabeni@...hat.com>,
        <netdev@...r.kernel.org>, <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] net: phy: at803x: add QCA8084 ethernet phy support



On 11/5/2023 3:35 AM, Russell King (Oracle) wrote:
> On Fri, Nov 03, 2023 at 08:35:37PM +0800, Luo Jie wrote:
>> Add qca8084 PHY support, which is four-port PHY with maximum
>> link capability 2.5G, the features of each port is almost same
>> as QCA8081 and slave seed config is not needed.
>>
>> There are some initialization configurations needed.
>> 1. Configuring qca8084 related initializations including
>> MSE detect threshold and ADC clock edge invert.
>> 2. Add the additional configurations for the CDT feature.
>>
>> Signed-off-by: Luo Jie <quic_luoj@...cinc.com>
>> ---
>>   drivers/net/phy/at803x.c | 40 +++++++++++++++++++++++++++++++++++++---
>>   1 file changed, 37 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c
>> index 37fb033e1c29..4124eb76d835 100644
>> --- a/drivers/net/phy/at803x.c
>> +++ b/drivers/net/phy/at803x.c
>> @@ -176,6 +176,8 @@
>>   #define AT8030_PHY_ID_MASK			0xffffffef
>>   
>>   #define QCA8081_PHY_ID				0x004dd101
>> +#define QCA8081_PHY_MASK			0xffffff00
>> +#define QCA8084_PHY_ID				0x004dd180
> ...
>> @@ -2207,8 +2240,9 @@ static struct phy_driver at803x_driver[] = {
>>   	.resume			= qca83xx_resume,
>>   }, {
>>   	/* Qualcomm QCA8081 */
>> -	PHY_ID_MATCH_EXACT(QCA8081_PHY_ID),
>> -	.name			= "Qualcomm QCA8081",
>> +	.phy_id			= QCA8081_PHY_ID,
>> +	.phy_id_mask		= QCA8081_PHY_MASK,
>> +	.name			= "Qualcomm QCA808X",
> ...
>> @@ -2241,7 +2275,7 @@ static struct mdio_device_id __maybe_unused atheros_tbl[] = {
>>   	{ PHY_ID_MATCH_EXACT(QCA8327_A_PHY_ID) },
>>   	{ PHY_ID_MATCH_EXACT(QCA8327_B_PHY_ID) },
>>   	{ PHY_ID_MATCH_EXACT(QCA9561_PHY_ID) },
>> -	{ PHY_ID_MATCH_EXACT(QCA8081_PHY_ID) },
>> +	{ QCA8081_PHY_ID, QCA8081_PHY_MASK},
> 
> So, in summary from the above, what you're doing is using the pair of
> QCA8081_PHY_ID, QCA8081_PHY_MASK to match not only QCA8081 but also
> QCA8084. This is confusing.

Yes, Russell.
qca8084 is the different PHY model compared with the existed qca8081, 
qca8084 needs the extra PCS configuration and clock configuration, which 
will be pushed to the PCS driver.

I will update to use PHY_ID_MATCH_MODEL for the new added entry of 
qca8084 to distinguish qca8081.

> 
> Are there any other parts that QCA808X would correspond with which
> would not be compatible with the above? E.g. QCA8082, QCA8083, QCA8088
> etc.

The new added PHY chip qca8082, qca8084 and qca8085 use the same PHY ID, 
so the PHY_ID_MATCH_MODEL should be able to cover the new added entry.

> 
> If there are, then the correct approach would be to list them
> separately in atheros_tbl, and also have separate driver entries in
> at803x_driver so it's unambiguous.
> 
> If we keep this approach, then I would suggest:
> 
> #define QCA808X_PHY_ID		0x004dd100
> #define QCA808X_PHY_MASK	GENMASK(31, 8)
> 
> to make it explicit that this phy ID/mask pair is matching several
> devices, rather than re-using the QCA8081_PHY_ID definition.

Thanks for the suggestion. the PHY_ID_MATCH_MODEL should match the new 
added PHY devices.

> 
> 
> The next point - what about the revision field which occupies bits 3:0
> in these:

bits[3:0] is for the revision number, currently there is only one PHY ID 
(revision number is 0)used for the new added series PHY chip.

> 
>>   static bool qca808x_has_fast_retrain_or_slave_seed(struct phy_device *phydev)
>>   {
>> +	if (phydev->phy_id == QCA8084_PHY_ID)
>> +		return false;
>> +
> ...
>> @@ -1767,6 +1781,20 @@ static int qca808x_config_init(struct phy_device *phydev)
>>   {
>>   	int ret;
>>   
>> +	if (phydev->phy_id == QCA8084_PHY_ID) {
>> +		/* Invert ADC clock edge */
> ...
>> @@ -1958,6 +1986,11 @@ static int qca808x_cable_test_start(struct phy_device *phydev)
>>   	phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807a, 0xc060);
>>   	phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807e, 0xb060);
>>   
>> +	if (phydev->phy_id == QCA8084_PHY_ID) {
> 
> Do these need to be exact matches, or should the revision field be
> ignored? If so, consider using phy_id_compare(), or if you end up with
> separate driver entries, consider using phydev_id_compare().
> 
> Thanks.
> 
Ok, i will double check this configuration to consider to use the 
suggested API in the next updated patch. Thanks Russell for the review.