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Message-ID: <ZUtP7lMqFnNK8lw_@hog>
Date: Wed, 8 Nov 2023 10:07:58 +0100
From: Sabrina Dubroca <sd@...asysnail.net>
To: Jakub Kicinski <kuba@...nel.org>
Cc: "Dae R. Jeong" <threeearcat@...il.com>, borisp@...dia.com,
john.fastabend@...il.com, davem@...emloft.net, edumazet@...gle.com,
pabeni@...hat.com, netdev@...r.kernel.org,
linux-kernel@...r.kernel.org, ywchoi@...ys.kaist.ac.kr
Subject: Re: Missing a write memory barrier in tls_init()
2023-11-07, 18:53:24 -0800, Jakub Kicinski wrote:
> On Tue, 7 Nov 2023 23:45:46 +0100 Sabrina Dubroca wrote:
> > Wouldn't it be enough to just move the rcu_assign_pointer after ctx is
> > fully initialized, ie just before update_sk_prot? also clearer wrt
> > RCU.
>
> I'm not sure, IIUC rcu_assign_pointer() is equivalent to
> WRITE_ONCE() on any sane architecture, it depends on address
> dependencies to provide ordering.
Not what the doc says:
/**
* rcu_assign_pointer() - assign to RCU-protected pointer
[...]
* Inserts memory barriers on architectures that require them
* (which is most of them), and also prevents the compiler from
* reordering the code that initializes the structure after the pointer
* assignment.
[...]
*/
And it uses smp_store_release (unless writing NULL).
rcu_dereference is the one that usually doesn't contain a barrier:
/**
* rcu_dereference_check() - rcu_dereference with debug checking
[...]
* Inserts memory barriers on architectures that require them
* (currently only the Alpha), prevents the compiler from refetching
* (and from merging fetches), and, more importantly, documents exactly
* which pointers are protected by RCU and checks that the pointer is
* annotated as __rcu.
*/
> Since here we care about
> ctx->sk_prot being updated, when changes to sk->sk_prot
> are visible there is no super-obvious address dependency.
>
> There may be one. But to me at least it isn't an obvious
> "RCU used right will handle this" case.
Ok, I think you're right. Looking at smp_store_release used by rcu_assign_pointer:
#define __smp_store_release(p, v) \
do { \
compiletime_assert_atomic_type(*p); \
barrier(); \
WRITE_ONCE(*p, v); \
} while (0)
it's only going to make sure ctx->sk_proto is set when ctx is visible,
and not guarantee that ctx is visible whenever sk->sk_prot has been
switched over.
--
Sabrina
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