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Message-ID: <gxods3yclaqkrud6jxhvcjm67vfp5zmuoxjlr6llcddny7zwsr@473g74uk36xn>
Date: Mon, 13 Nov 2023 18:05:13 +0300
From: Serge Semin <fancer.lancer@...il.com>
To: Yanteng Si <siyanteng@...ngson.cn>
Cc: andrew@...n.ch, hkallweit1@...il.com, peppe.cavallaro@...com,
alexandre.torgue@...s.st.com, joabreu@...opsys.com, Jose.Abreu@...opsys.com,
chenhuacai@...ngson.cn, linux@...linux.org.uk, dongbiao@...ngson.cn,
guyinggang@...ngson.cn, netdev@...r.kernel.org, loongarch@...ts.linux.dev,
chris.chenfeiyang@...il.com
Subject: Re: [PATCH v5 3/9] net: stmmac: Add Loongson DWGMAC definitions
On Fri, Nov 10, 2023 at 05:25:42PM +0800, Yanteng Si wrote:
> Loongson platforms use a DWGMAC which supports multi-channel.
>
> There are two types of Loongson DWGMAC. The first type shares the same
> register definitions and has similar logic as dwmac1000. The second type
> uses several different register definitions.
>
> Signed-off-by: Yanteng Si <siyanteng@...ngson.cn>
> Signed-off-by: Feiyang Chen <chenfeiyang@...ngson.cn>
> Signed-off-by: Yinggang Gu <guyinggang@...ngson.cn>
> ---
> drivers/net/ethernet/stmicro/stmmac/common.h | 1 +
> .../ethernet/stmicro/stmmac/dwmac1000_dma.c | 63 ++++++++++++++++---
> .../net/ethernet/stmicro/stmmac/dwmac_dma.h | 57 ++++++++++++++++-
> .../net/ethernet/stmicro/stmmac/dwmac_lib.c | 39 ++++++------
> drivers/net/ethernet/stmicro/stmmac/hwif.c | 3 +-
> .../net/ethernet/stmicro/stmmac/stmmac_main.c | 2 +
> 6 files changed, 133 insertions(+), 32 deletions(-)
>
> diff --git a/drivers/net/ethernet/stmicro/stmmac/common.h b/drivers/net/ethernet/stmicro/stmmac/common.h
> index e3f650e88f82..e01584fe9efa 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/common.h
> +++ b/drivers/net/ethernet/stmicro/stmmac/common.h
> @@ -34,6 +34,7 @@
> #define DWMAC_CORE_5_00 0x50
> #define DWMAC_CORE_5_10 0x51
> #define DWMAC_CORE_5_20 0x52
> +#define DWGMAC_CORE_1_00 0x10
Name is ambiguous. All of the DWMAC_CORE_* macro above also refer to
the DW GMACs. Moreover generic DW MAC IP-core v1 I guess never existed
in a way the driver expects it. So IMO it would be better for you to
drop this and just add a new flag to the plat_stmmacenet_data
structure (extended_desc or has_lson/STMMAC_FLAG_HAS_LSON).
* One more time took a look at the plat_stmmacenet_data structure and
* scared of the mess it has evolved to.
> #define DWXGMAC_CORE_2_10 0x21
> #define DWXGMAC_CORE_2_20 0x22
> #define DWXLGMAC_CORE_2_00 0x20
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c
> index ce0e6ca6f3a2..234d30c5a836 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c
> @@ -12,7 +12,8 @@
> Author: Giuseppe Cavallaro <peppe.cavallaro@...com>
> *******************************************************************************/
>
> -#include <asm/io.h>
> +#include <linux/io.h>
> +#include "stmmac.h"
> #include "dwmac1000.h"
> #include "dwmac_dma.h"
>
> @@ -111,13 +112,58 @@ static void dwmac1000_dma_init(struct stmmac_priv *priv, void __iomem *ioaddr,
> writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_INTR_ENA);
> }
>
> +static void dwmac1000_dma_init_channel(struct stmmac_priv *priv,
> + void __iomem *ioaddr,
> + struct stmmac_dma_cfg *dma_cfg, u32 chan)
> +{
> + u32 value;
> + int txpbl = dma_cfg->txpbl ?: dma_cfg->pbl;
> + int rxpbl = dma_cfg->rxpbl ?: dma_cfg->pbl;
> +
> + if (!(priv->plat->flags & STMMAC_FLAG_MULTI_MSI_EN))
> + return;
Use dma_cfg->multi_msi_en in a way it's done in the DW GMAC v4*
module. Also note this flag isn't something that should block all the
DMA-channel-specific setups. It's intended to activate the per-channel
IRQs instead of raising the generic MAC IRQ for all the events.
> +
> + /* common channel control register config */
> + value = readl(ioaddr + DMA_CHAN_BUS_MODE(chan));
> +
> + /* Set the DMA PBL (Programmable Burst Length) mode.
> + *
> + * Note: before stmmac core 3.50 this mode bit was 4xPBL, and
> + * post 3.5 mode bit acts as 8*PBL.
> + */
> + if (dma_cfg->pblx8)
> + value |= DMA_BUS_MODE_MAXPBL;
> + value |= DMA_BUS_MODE_USP;
> + value &= ~(DMA_BUS_MODE_PBL_MASK | DMA_BUS_MODE_RPBL_MASK);
> + value |= (txpbl << DMA_BUS_MODE_PBL_SHIFT);
> + value |= (rxpbl << DMA_BUS_MODE_RPBL_SHIFT);
> +
> + /* Set the Fixed burst mode */
> + if (dma_cfg->fixed_burst)
> + value |= DMA_BUS_MODE_FB;
> +
> + /* Mixed Burst has no effect when fb is set */
> + if (dma_cfg->mixed_burst)
> + value |= DMA_BUS_MODE_MB;
> +
> + value |= DMA_BUS_MODE_ATDS;
> +
> + if (dma_cfg->aal)
> + value |= DMA_BUS_MODE_AAL;
> +
> + writel(value, ioaddr + DMA_CHAN_BUS_MODE(chan));
> +
> + /* Mask interrupts by writing to CSR7 */
> + writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_CHAN_INTR_ENA(chan));
> +}
This is just a multi-channel copy of the dwmac1000_dma_init(). Please
factor out all the channel-specific setups to the
dwmac1000_dma_init_channel() method and all the generic setups (if
any) to the dwmac1000_dma_init() function.
> +
> static void dwmac1000_dma_init_rx(struct stmmac_priv *priv,
> void __iomem *ioaddr,
> struct stmmac_dma_cfg *dma_cfg,
> dma_addr_t dma_rx_phy, u32 chan)
> {
> /* RX descriptor base address list must be written into DMA CSR3 */
> - writel(lower_32_bits(dma_rx_phy), ioaddr + DMA_RCV_BASE_ADDR);
> + writel(lower_32_bits(dma_rx_phy), ioaddr + DMA_CHAN_RCV_BASE_ADDR(chan));
> }
>
> static void dwmac1000_dma_init_tx(struct stmmac_priv *priv,
> @@ -126,7 +172,7 @@ static void dwmac1000_dma_init_tx(struct stmmac_priv *priv,
> dma_addr_t dma_tx_phy, u32 chan)
> {
> /* TX descriptor base address list must be written into DMA CSR4 */
> - writel(lower_32_bits(dma_tx_phy), ioaddr + DMA_TX_BASE_ADDR);
> + writel(lower_32_bits(dma_tx_phy), ioaddr + DMA_CHAN_TX_BASE_ADDR(chan));
> }
>
> static u32 dwmac1000_configure_fc(u32 csr6, int rxfifosz)
> @@ -154,7 +200,7 @@ static void dwmac1000_dma_operation_mode_rx(struct stmmac_priv *priv,
> void __iomem *ioaddr, int mode,
> u32 channel, int fifosz, u8 qmode)
> {
> - u32 csr6 = readl(ioaddr + DMA_CONTROL);
> + u32 csr6 = readl(ioaddr + DMA_CHAN_CONTROL(channel));
>
> if (mode == SF_DMA_MODE) {
> pr_debug("GMAC: enable RX store and forward mode\n");
> @@ -176,14 +222,14 @@ static void dwmac1000_dma_operation_mode_rx(struct stmmac_priv *priv,
> /* Configure flow control based on rx fifo size */
> csr6 = dwmac1000_configure_fc(csr6, fifosz);
>
> - writel(csr6, ioaddr + DMA_CONTROL);
> + writel(csr6, ioaddr + DMA_CHAN_CONTROL(channel));
> }
>
> static void dwmac1000_dma_operation_mode_tx(struct stmmac_priv *priv,
> void __iomem *ioaddr, int mode,
> u32 channel, int fifosz, u8 qmode)
> {
> - u32 csr6 = readl(ioaddr + DMA_CONTROL);
> + u32 csr6 = readl(ioaddr + DMA_CHAN_CONTROL(channel));
>
> if (mode == SF_DMA_MODE) {
> pr_debug("GMAC: enable TX store and forward mode\n");
> @@ -210,7 +256,7 @@ static void dwmac1000_dma_operation_mode_tx(struct stmmac_priv *priv,
> csr6 |= DMA_CONTROL_TTC_256;
> }
>
> - writel(csr6, ioaddr + DMA_CONTROL);
> + writel(csr6, ioaddr + DMA_CHAN_CONTROL(channel));
> }
>
> static void dwmac1000_dump_dma_regs(struct stmmac_priv *priv,
> @@ -273,12 +319,13 @@ static int dwmac1000_get_hw_feature(struct stmmac_priv *priv,
> static void dwmac1000_rx_watchdog(struct stmmac_priv *priv,
> void __iomem *ioaddr, u32 riwt, u32 queue)
> {
> - writel(riwt, ioaddr + DMA_RX_WATCHDOG);
> + writel(riwt, ioaddr + DMA_CHAN_RX_WATCHDOG(queue));
> }
>
> const struct stmmac_dma_ops dwmac1000_dma_ops = {
> .reset = dwmac_dma_reset,
> .init = dwmac1000_dma_init,
> + .init_chan = dwmac1000_dma_init_channel,
> .init_rx_chan = dwmac1000_dma_init_rx,
> .init_tx_chan = dwmac1000_dma_init_tx,
> .axi = dwmac1000_dma_axi,
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac_dma.h b/drivers/net/ethernet/stmicro/stmmac/dwmac_dma.h
> index 77141391bd2f..90464e1c9649 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac_dma.h
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac_dma.h
> @@ -76,8 +76,15 @@
> #define DMA_INTR_ENA_RIE 0x00000040 /* Receive Interrupt */
> #define DMA_INTR_ENA_ERE 0x00004000 /* Early Receive */
>
> +#define DMA_INTR_ENA_NIE_LOONGSON 0x00060000 /* Loongson Normal Summary */
> +
> +#ifdef CONFIG_DWMAC_LOONGSON
> +#define DMA_INTR_NORMAL (DMA_INTR_ENA_NIE_LOONGSON | DMA_INTR_ENA_NIE | \
Emm, I don't understand this:
DMA_INTR_ENA_NIE = 0x00010000
DMA_INTR_ENA_NIE_LOONGSON = 0x00060000
What are these additional NIE flags and why do you call them also NIE?
> + DMA_INTR_ENA_RIE | DMA_INTR_ENA_TIE)
> +#else
> #define DMA_INTR_NORMAL (DMA_INTR_ENA_NIE | DMA_INTR_ENA_RIE | \
> DMA_INTR_ENA_TIE)
> +#endif
>
> /* DMA Abnormal interrupt */
> #define DMA_INTR_ENA_AIE 0x00008000 /* Abnormal Summary */
> @@ -91,8 +98,15 @@
> #define DMA_INTR_ENA_TJE 0x00000008 /* Transmit Jabber */
> #define DMA_INTR_ENA_TSE 0x00000002 /* Transmit Stopped */
>
> +#define DMA_INTR_ENA_AIE_LOONGSON 0x00018000 /* Loongson Abnormal Summary */
> +
> +#ifdef CONFIG_DWMAC_LOONGSON
> +#define DMA_INTR_ABNORMAL (DMA_INTR_ENA_AIE_LOONGSON | DMA_INTR_ENA_AIE | \
Similarly I don't understand this.
DMA_INTR_ENA_AIE = 0x00008000
DMA_INTR_ENA_AIE_LOONGSON = 0x00018000
so it's Loongson-specific needs normal DMA_INTR_ENA_AIE and some
additional flag enabled. What is the meaning of that flag?
> + DMA_INTR_ENA_FBE | DMA_INTR_ENA_UNE)
> +#else
> #define DMA_INTR_ABNORMAL (DMA_INTR_ENA_AIE | DMA_INTR_ENA_FBE | \
> DMA_INTR_ENA_UNE)
> +#endif
>
> /* DMA default interrupt mask */
> #define DMA_INTR_DEFAULT_MASK (DMA_INTR_NORMAL | DMA_INTR_ABNORMAL)
> @@ -128,9 +142,29 @@
> #define DMA_STATUS_TI 0x00000001 /* Transmit Interrupt */
> #define DMA_CONTROL_FTF 0x00100000 /* Flush transmit FIFO */
>
> -#define DMA_STATUS_MSK_COMMON (DMA_STATUS_NIS | \
> - DMA_STATUS_AIS | \
> - DMA_STATUS_FBI)
> +#define DMA_STATUS_TX_NIS_LOONGSON 0x00040000 /* Normal Tx Interrupt Summary */
> +#define DMA_STATUS_RX_NIS_LOONGSON 0x00020000 /* Normal Rx Interrupt Summary */
> +#define DMA_STATUS_TX_AIS_LOONGSON 0x00010000 /* Abnormal Tx Interrupt Summary */
> +#define DMA_STATUS_RX_AIS_LOONGSON 0x00008000 /* Abnormal Rx Interrupt Summary */
> +#define DMA_STATUS_TX_FBI_LOONGSON 0x00002000 /* Fatal Tx Bus Error Interrupt */
> +#define DMA_STATUS_RX_FBI_LOONGSON 0x00001000 /* Fatal Rx Bus Error Interrupt */
> +
> +#ifdef CONFIG_DWMAC_LOONGSON
> +#define DMA_NOR_INTR_STATUS (DMA_STATUS_TX_NIS_LOONGSON | DMA_STATUS_RX_NIS_LOONGSON)
> +#define DMA_ABNOR_INTR_STATUS (DMA_STATUS_TX_AIS_LOONGSON | DMA_STATUS_RX_AIS_LOONGSON)
> +#define DMA_FB_INTR_STATUS (DMA_STATUS_TX_FBI_LOONGSON | DMA_STATUS_RX_FBI_LOONGSON)
> +#else
> +#define DMA_NOR_INTR_STATUS DMA_STATUS_NIS
> +#define DMA_ABNOR_INTR_STATUS DMA_STATUS_AIS
> +#define DMA_FB_INTR_STATUS DMA_STATUS_FBI
> +#endif
In addition to what said Andrew, this looks incorrect since the
Loongson flags intersect the generic status flags. So it seems like
at least the statistics handling or the
show_rx_process_state()/show_tx_process_state() won't work correctly.
-Serge(y)
> +
> +#define DMA_INTR_STATUS (DMA_STATUS_GPI | \
> + DMA_STATUS_GMI | \
> + DMA_STATUS_GLI)
> +#define DMA_STATUS_MSK_COMMON (DMA_NOR_INTR_STATUS | \
> + DMA_ABNOR_INTR_STATUS | \
> + DMA_FB_INTR_STATUS)
>
> #define DMA_STATUS_MSK_RX (DMA_STATUS_ERI | \
> DMA_STATUS_RWT | \
> @@ -148,6 +182,9 @@
> DMA_STATUS_TI | \
> DMA_STATUS_MSK_COMMON)
>
> +/* Following DMA defines are chanels oriented */
> +#define DMA_CHAN_OFFSET 0x100
> +
> #define NUM_DWMAC100_DMA_REGS 9
> #define NUM_DWMAC1000_DMA_REGS 23
> #define NUM_DWMAC4_DMA_REGS 27
> @@ -170,4 +207,18 @@ int dwmac_dma_interrupt(struct stmmac_priv *priv, void __iomem *ioaddr,
> struct stmmac_extra_stats *x, u32 chan, u32 dir);
> int dwmac_dma_reset(struct stmmac_priv *priv, void __iomem *ioaddr);
>
> +static inline u32 dma_chan_base_addr(u32 base, u32 chan)
> +{
> + return base + chan * DMA_CHAN_OFFSET;
> +}
> +
> +#define DMA_CHAN_XMT_POLL_DEMAND(chan) dma_chan_base_addr(DMA_XMT_POLL_DEMAND, chan)
> +#define DMA_CHAN_INTR_ENA(chan) dma_chan_base_addr(DMA_INTR_ENA, chan)
> +#define DMA_CHAN_CONTROL(chan) dma_chan_base_addr(DMA_CONTROL, chan)
> +#define DMA_CHAN_STATUS(chan) dma_chan_base_addr(DMA_STATUS, chan)
> +#define DMA_CHAN_BUS_MODE(chan) dma_chan_base_addr(DMA_BUS_MODE, chan)
> +#define DMA_CHAN_RCV_BASE_ADDR(chan) dma_chan_base_addr(DMA_RCV_BASE_ADDR, chan)
> +#define DMA_CHAN_TX_BASE_ADDR(chan) dma_chan_base_addr(DMA_TX_BASE_ADDR, chan)
> +#define DMA_CHAN_RX_WATCHDOG(chan) dma_chan_base_addr(DMA_RX_WATCHDOG, chan)
> +
> #endif /* __DWMAC_DMA_H__ */
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c b/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c
> index 0cb337ffb7ac..c36aec97bbb5 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c
> @@ -31,63 +31,63 @@ int dwmac_dma_reset(struct stmmac_priv *priv, void __iomem *ioaddr)
> void dwmac_enable_dma_transmission(struct stmmac_priv *priv,
> void __iomem *ioaddr, u32 chan)
> {
> - writel(1, ioaddr + DMA_XMT_POLL_DEMAND);
> + writel(1, ioaddr + DMA_CHAN_XMT_POLL_DEMAND(chan));
> }
>
> void dwmac_enable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr,
> u32 chan, bool rx, bool tx)
> {
> - u32 value = readl(ioaddr + DMA_INTR_ENA);
> + u32 value = readl(ioaddr + DMA_CHAN_INTR_ENA(chan));
>
> if (rx)
> value |= DMA_INTR_DEFAULT_RX;
> if (tx)
> value |= DMA_INTR_DEFAULT_TX;
>
> - writel(value, ioaddr + DMA_INTR_ENA);
> + writel(value, ioaddr + DMA_CHAN_INTR_ENA(chan));
> }
>
> void dwmac_disable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr,
> u32 chan, bool rx, bool tx)
> {
> - u32 value = readl(ioaddr + DMA_INTR_ENA);
> + u32 value = readl(ioaddr + DMA_CHAN_INTR_ENA(chan));
>
> if (rx)
> value &= ~DMA_INTR_DEFAULT_RX;
> if (tx)
> value &= ~DMA_INTR_DEFAULT_TX;
>
> - writel(value, ioaddr + DMA_INTR_ENA);
> + writel(value, ioaddr + DMA_CHAN_INTR_ENA(chan));
> }
>
> void dwmac_dma_start_tx(struct stmmac_priv *priv, void __iomem *ioaddr,
> u32 chan)
> {
> - u32 value = readl(ioaddr + DMA_CONTROL);
> + u32 value = readl(ioaddr + DMA_CHAN_CONTROL(chan));
> value |= DMA_CONTROL_ST;
> - writel(value, ioaddr + DMA_CONTROL);
> + writel(value, ioaddr + DMA_CHAN_CONTROL(chan));
> }
>
> void dwmac_dma_stop_tx(struct stmmac_priv *priv, void __iomem *ioaddr, u32 chan)
> {
> - u32 value = readl(ioaddr + DMA_CONTROL);
> + u32 value = readl(ioaddr + DMA_CHAN_CONTROL(chan));
> value &= ~DMA_CONTROL_ST;
> - writel(value, ioaddr + DMA_CONTROL);
> + writel(value, ioaddr + DMA_CHAN_CONTROL(chan));
> }
>
> void dwmac_dma_start_rx(struct stmmac_priv *priv, void __iomem *ioaddr,
> u32 chan)
> {
> - u32 value = readl(ioaddr + DMA_CONTROL);
> + u32 value = readl(ioaddr + DMA_CHAN_CONTROL(chan));
> value |= DMA_CONTROL_SR;
> - writel(value, ioaddr + DMA_CONTROL);
> + writel(value, ioaddr + DMA_CHAN_CONTROL(chan));
> }
>
> void dwmac_dma_stop_rx(struct stmmac_priv *priv, void __iomem *ioaddr, u32 chan)
> {
> - u32 value = readl(ioaddr + DMA_CONTROL);
> + u32 value = readl(ioaddr + DMA_CHAN_CONTROL(chan));
> value &= ~DMA_CONTROL_SR;
> - writel(value, ioaddr + DMA_CONTROL);
> + writel(value, ioaddr + DMA_CHAN_CONTROL(chan));
> }
>
> #ifdef DWMAC_DMA_DEBUG
> @@ -167,7 +167,7 @@ int dwmac_dma_interrupt(struct stmmac_priv *priv, void __iomem *ioaddr,
> struct stmmac_txq_stats *txq_stats = &priv->xstats.txq_stats[chan];
> int ret = 0;
> /* read the status register (CSR5) */
> - u32 intr_status = readl(ioaddr + DMA_STATUS);
> + u32 intr_status = readl(ioaddr + DMA_CHAN_STATUS(chan));
>
> #ifdef DWMAC_DMA_DEBUG
> /* Enable it to monitor DMA rx/tx status in case of critical problems */
> @@ -182,7 +182,7 @@ int dwmac_dma_interrupt(struct stmmac_priv *priv, void __iomem *ioaddr,
> intr_status &= DMA_STATUS_MSK_TX;
>
> /* ABNORMAL interrupts */
> - if (unlikely(intr_status & DMA_STATUS_AIS)) {
> + if (unlikely(intr_status & DMA_ABNOR_INTR_STATUS)) {
> if (unlikely(intr_status & DMA_STATUS_UNF)) {
> ret = tx_hard_error_bump_tc;
> x->tx_undeflow_irq++;
> @@ -205,13 +205,13 @@ int dwmac_dma_interrupt(struct stmmac_priv *priv, void __iomem *ioaddr,
> x->tx_process_stopped_irq++;
> ret = tx_hard_error;
> }
> - if (unlikely(intr_status & DMA_STATUS_FBI)) {
> + if (unlikely(intr_status & DMA_FB_INTR_STATUS)) {
> x->fatal_bus_error_irq++;
> ret = tx_hard_error;
> }
> }
> /* TX/RX NORMAL interrupts */
> - if (likely(intr_status & DMA_STATUS_NIS)) {
> + if (likely(intr_status & DMA_NOR_INTR_STATUS)) {
> if (likely(intr_status & DMA_STATUS_RI)) {
> u32 value = readl(ioaddr + DMA_INTR_ENA);
> /* to schedule NAPI on real RIE event. */
> @@ -232,12 +232,11 @@ int dwmac_dma_interrupt(struct stmmac_priv *priv, void __iomem *ioaddr,
> x->rx_early_irq++;
> }
> /* Optional hardware blocks, interrupts should be disabled */
> - if (unlikely(intr_status &
> - (DMA_STATUS_GPI | DMA_STATUS_GMI | DMA_STATUS_GLI)))
> + if (unlikely(intr_status & DMA_INTR_STATUS))
> pr_warn("%s: unexpected status %08x\n", __func__, intr_status);
>
> /* Clear the interrupt by writing a logic 1 to the CSR5[15-0] */
> - writel((intr_status & 0x1ffff), ioaddr + DMA_STATUS);
> + writel((intr_status & 0x7ffff), ioaddr + DMA_CHAN_STATUS(chan));
>
> return ret;
> }
> diff --git a/drivers/net/ethernet/stmicro/stmmac/hwif.c b/drivers/net/ethernet/stmicro/stmmac/hwif.c
> index 93cead5613e3..e5e7ac03459d 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/hwif.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/hwif.c
> @@ -58,7 +58,8 @@ static int stmmac_dwmac1_quirks(struct stmmac_priv *priv)
> dev_info(priv->device, "Enhanced/Alternate descriptors\n");
>
> /* GMAC older than 3.50 has no extended descriptors */
> - if (priv->synopsys_id >= DWMAC_CORE_3_50) {
> + if (priv->synopsys_id >= DWMAC_CORE_3_50 ||
> + priv->synopsys_id == DWGMAC_CORE_1_00) {
> dev_info(priv->device, "Enabled extended descriptors\n");
> priv->extend_desc = 1;
> } else {
> diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
> index 7371713c116d..aafc75fa14a0 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
> @@ -7062,6 +7062,7 @@ static int stmmac_hw_init(struct stmmac_priv *priv)
> /* dwmac-sun8i only work in chain mode */
> if (priv->plat->flags & STMMAC_FLAG_HAS_SUN8I)
> chain_mode = 1;
> +
> priv->chain_mode = chain_mode;
>
> /* Initialize HW Interface */
> @@ -7142,6 +7143,7 @@ static int stmmac_hw_init(struct stmmac_priv *priv)
> * riwt_off field from the platform.
> */
> if (((priv->synopsys_id >= DWMAC_CORE_3_50) ||
> + (priv->synopsys_id == DWGMAC_CORE_1_00) ||
> (priv->plat->has_xgmac)) && (!priv->plat->riwt_off)) {
> priv->use_riwt = 1;
> dev_info(priv->device,
> --
> 2.31.4
>
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