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Message-ID: <20231114134315.GA1645963-robh@kernel.org>
Date: Tue, 14 Nov 2023 07:43:15 -0600
From: Rob Herring <robh@...nel.org>
To: Daniel Golle <daniel@...rotopia.org>
Cc: "David S. Miller" <davem@...emloft.net>, Eric Dumazet <edumazet@...gle.com>,
Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>, Conor Dooley <conor+dt@...nel.org>,
Chunfeng Yun <chunfeng.yun@...iatek.com>, Vinod Koul <vkoul@...nel.org>,
Kishon Vijay Abraham I <kishon@...nel.org>, Felix Fietkau <nbd@....name>, John Crispin <john@...ozen.org>,
Sean Wang <sean.wang@...iatek.com>, Mark Lee <Mark-MC.Lee@...iatek.com>,
Lorenzo Bianconi <lorenzo@...nel.org>, Matthias Brugger <matthias.bgg@...il.com>,
AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>, Andrew Lunn <andrew@...n.ch>,
Heiner Kallweit <hkallweit1@...il.com>, Russell King <linux@...linux.org.uk>,
Alexander Couzens <lynxis@...0.eu>, Philipp Zabel <p.zabel@...gutronix.de>, netdev@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-mediatek@...ts.infradead.org,
linux-phy@...ts.infradead.org
Subject: Re: [RFC PATCH 1/8] dt-bindings: phy: mediatek,xfi-pextp: add new
bindings
On Thu, Nov 09, 2023 at 09:50:55PM +0000, Daniel Golle wrote:
> Add bindings for the MediaTek PEXTP Ethernet SerDes PHY found in the
> MediaTek MT7988 SoC which can operate at various interfaces modes:
>
> * USXGMII
> * 10GBase-R
> * 5GBase-R
> * 2500Base-X
> * 1000Base-X
> * Cisco SGMII (MAC side)
>
> Signed-off-by: Daniel Golle <daniel@...rotopia.org>
> ---
> .../bindings/phy/mediatek,xfi-pextp.yaml | 71 +++++++++++++++++++
> 1 file changed, 71 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/mediatek,xfi-pextp.yaml
>
> diff --git a/Documentation/devicetree/bindings/phy/mediatek,xfi-pextp.yaml b/Documentation/devicetree/bindings/phy/mediatek,xfi-pextp.yaml
> new file mode 100644
> index 0000000000000..948d5031af1e3
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/mediatek,xfi-pextp.yaml
> @@ -0,0 +1,71 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/mediatek,xfi-pextp.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: MediaTek XFI PEXTP SerDes PHY
> +
> +maintainers:
> + - Daniel Golle <daniel@...rotopia.org>
> +
> +description: |
Don't need '|' here.
> + The MediaTek XFI PEXTP SerDes PHY provides the physical SerDes lanes
> + used by the MediaTek USXGMII PCS.
> +
> +properties:
> + $nodename:
> + pattern: "^phy@[0-9a-f]+$"
> +
> + compatible:
> + const: mediatek,mt7988-xfi-pextp
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + items:
> + - description: XFI PHY clock
> +
> + resets:
> + items:
> + - description: PEXTP reset
> +
> + mediatek,usxgmii-performance-errata:
> + $ref: /schemas/types.yaml#/definitions/flag
> + description:
> + USXGMII0 on MT7988 suffers from a performance problem in 10GBase-R
> + mode which needs a work-around in the driver. The work-around is
> + enabled using this flag.
> +
> + "#phy-cells":
> + const: 0
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - resets
> + - "#phy-cells"
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/mediatek,mt7988-clk.h>
> + #include <dt-bindings/reset/mediatek,mt7988-resets.h>
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + xfi_pextp0: phy@...20000 {
Drop unused labels.
> + compatible = "mediatek,mt7988-xfi-pextp";
> + reg = <0 0x11f20000 0 0x10000>;
> + clocks = <&topckgen CLK_TOP_XFI_PHY_0_XTAL_SEL>;
> + resets = <&watchdog MT7988_TOPRGU_XFI_PEXTP0_GRST>;
> + mediatek,usxgmii-performance-errata;
> + #phy-cells = <0>;
> + };
> + };
> +
> +...
> --
> 2.42.1
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