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Date: Wed, 15 Nov 2023 15:35:54 +0100
From: Andrew Lunn <andrew@...n.ch>
To: Luo Jie <quic_luoj@...cinc.com>
Cc: agross@...nel.org, andersson@...nel.org, konrad.dybcio@...aro.org,
	davem@...emloft.net, edumazet@...gle.com, kuba@...nel.org,
	pabeni@...hat.com, robh+dt@...nel.org,
	krzysztof.kozlowski+dt@...aro.org, conor+dt@...nel.org,
	hkallweit1@...il.com, linux@...linux.org.uk,
	robert.marko@...tura.hr, linux-arm-msm@...r.kernel.org,
	netdev@...r.kernel.org, devicetree@...r.kernel.org,
	linux-kernel@...r.kernel.org, quic_srichara@...cinc.com
Subject: Re: [PATCH 9/9] dt-bindings: net: ipq4019-mdio: Document ipq5332
 platform

> +  phy-reset-gpio:
> +    minItems: 1
> +    maxItems: 3
> +    description:
> +      GPIO used to reset the PHY, each GPIO is for resetting the connected
> +      ethernet PHY device.

This is a PHY property, so should be in the PHY node. phylib should
then take care of fit.

> +
> +  phyaddr-fixup:
> +    description: Register address for programing MDIO address of PHY devices

Please give a better description of this and the next two properties.

> +
> +  pcsaddr-fixup:
> +    description: Register address for programing MDIO address of PCS devices
> +
> +  mdio-clk-fixup:
> +    description: The initialization clocks to be configured
> +
> +  fixup:
> +    description: The MDIO address of PHY/PCS device to be programed
> +        clocks:
> +          items:
> +            - description: MDIO clock source frequency fixed to 100MHZ
> +            - description: UNIPHY0 AHB clock source frequency fixed to 100MHZ
> +            - description: UNIPHY0 SYS clock source frequency fixed to 24MHZ
> +            - description: UNIPHY1 AHB clock source frequency fixed to 100MHZ
> +            - description: UNIPHY1 SYS clock source frequency fixed to 24MHZ

The clock frequencies is not relevent here, the driver sets that up.

    Andrew

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