netdev - Re: [PATCH net-next v3 1/8] dt-bindings: net: Introduce the Qualcomm IPQESS Ethernet switch

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Message-ID: <c8f721b5-4f66-4e38-b8ab-ee71b55c1a32@linaro.org>
Date: Thu, 16 Nov 2023 13:22:02 +0100
From: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To: Romain Gantois <romain.gantois@...tlin.com>, davem@...emloft.net,
 Rob Herring <robh+dt@...nel.org>,
 Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>
Cc: Jakub Kicinski <kuba@...nel.org>, Eric Dumazet <edumazet@...gle.com>,
 Paolo Abeni <pabeni@...hat.com>, netdev@...r.kernel.org,
 linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
 thomas.petazzoni@...tlin.com, Andrew Lunn <andrew@...n.ch>,
 Florian Fainelli <f.fainelli@...il.com>,
 Heiner Kallweit <hkallweit1@...il.com>, Russell King
 <linux@...linux.org.uk>, linux-arm-kernel@...ts.infradead.org,
 Vladimir Oltean <vladimir.oltean@....com>,
 Luka Perkov <luka.perkov@...tura.hr>, Robert Marko
 <robert.marko@...tura.hr>, Andy Gross <agross@...nel.org>,
 Bjorn Andersson <andersson@...nel.org>,
 Konrad Dybcio <konrad.dybcio@...ainline.org>
Subject: Re: [PATCH net-next v3 1/8] dt-bindings: net: Introduce the Qualcomm
 IPQESS Ethernet switch

On 14/11/2023 11:55, Romain Gantois wrote:
> Add the DT binding for the IPQESS Ethernet switch subsystem, that
> integrates a modified QCA8K switch and an EDMA MAC controller. It inherits
> from a basic ethernet switch binding and adds three regmaps, a phandle and
> reset line for the PSGMII, a phandle to the MDIO bus, a clock, and 32
> interrupts.
> 
> Signed-off-by: Romain Gantois <romain.gantois@...tlin.com>
> ---
>  .../bindings/net/qcom,ipq4019-ess.yaml        | 152 ++++++++++++++++++
>  1 file changed, 152 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/net/qcom,ipq4019-ess.yaml
> 
> diff --git a/Documentation/devicetree/bindings/net/qcom,ipq4019-ess.yaml b/Documentation/devicetree/bindings/net/qcom,ipq4019-ess.yaml
> new file mode 100644
> index 000000000000..85dff85e50b5
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/net/qcom,ipq4019-ess.yaml
> @@ -0,0 +1,152 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/net/qcom,ipq4019-ess.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm IPQ4019 Ethernet Switch Subsystem
> +
> +maintainers:
> +  - Romain Gantois <romain.gantois@...tlin.com>
> +
> +$ref: ethernet-switch.yaml#
> +
> +properties:
> +  compatible:
> +    const: qcom,ipq4019-ess
> +
> +  reg:
> +    items:
> +      - description: Base ESS registers, which configure the integrated QCA8K switch.
> +      - description: ESS PSGMII-related registers, which control VCO calibration and link
> +                     modes.
> +      - description: ESS EDMA controller registers. The EDMA controller is an Ethernet
> +                     controller connected to the integrated switch's CPU port.

Blank line

> +  reg-names:
> +    items:
> +      - const: base
> +      - const: psgmii_phy
> +      - const: edma
> +
> +  resets:
> +    items:
> +      - description: Handle to the PSGMII reset line.

Don't describe Devicetree, so handle (assuming you speak about phandle)
is redundant, so:
PSGMII reset line

If it is some other handle, please explain.

But then isn't PSGMII reset property of MDIO or PHY? It looks like you
add here properties from the PHY...

> +      - description: Handle to the ESS reset line.

ESS reset line


> +
> +  reset-names:
> +    items:
> +      - const: psgmii
> +      - const: ess
> +
> +  clocks:
> +    maxItems: 1
> +    description: Handle to the GCC ESS clock

Drop description.

> +
> +  mdio:
> +    maxItems: 1
> +    description: Handle to the IPQ4019 MDIO Controller
> +
> +  interrupts:
> +    maxItems: 32
> +    description: One interrupt per tx and rx queue, the first 16 are rx queues
> +                 and the last 16 are the tx queues
> +

Best regards,
Krzysztof