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Message-ID: <20231116135416.3371367-5-Raju.Rangoju@amd.com>
Date: Thu, 16 Nov 2023 19:24:16 +0530
From: Raju Rangoju <Raju.Rangoju@....com>
To: <netdev@...r.kernel.org>
CC: <davem@...emloft.net>, <edumazet@...gle.com>, <kuba@...nel.org>,
<pabeni@...hat.com>, <Shyam-sundar.S-k@....com>, Raju Rangoju
<Raju.Rangoju@....com>
Subject: [PATCH v2 net-next 4/4] amd-xgbe: use smn functions to avoid race
Some of the ethernet add-in-cards have dual PHY but share a single MDIO
line (between the ports). In such cases, link inconsistencies are
noticed during the heavy traffic and during reboot stress tests.
So, use the SMN calls to avoid the race conditions.
Signed-off-by: Raju Rangoju <Raju.Rangoju@....com>
---
drivers/net/ethernet/amd/xgbe/xgbe-dev.c | 36 ++++++++----------------
drivers/net/ethernet/amd/xgbe/xgbe-pci.c | 13 +++++----
drivers/net/ethernet/amd/xgbe/xgbe.h | 2 +-
3 files changed, 20 insertions(+), 31 deletions(-)
diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-dev.c b/drivers/net/ethernet/amd/xgbe/xgbe-dev.c
index a9eb2ffa9f73..1f43456442e5 100644
--- a/drivers/net/ethernet/amd/xgbe/xgbe-dev.c
+++ b/drivers/net/ethernet/amd/xgbe/xgbe-dev.c
@@ -125,6 +125,10 @@
#include "xgbe.h"
#include "xgbe-common.h"
+#ifdef CONFIG_X86
+#include <asm/amd_nb.h>
+#endif
+
static inline unsigned int xgbe_get_max_frame(struct xgbe_prv_data *pdata)
{
return pdata->netdev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
@@ -1170,14 +1174,9 @@ static int xgbe_read_mmd_regs_v3(struct xgbe_prv_data *pdata, int prtad,
int mmd_reg)
{
unsigned int mmd_address, index, offset;
- struct pci_dev *rdev;
unsigned long flags;
int mmd_data;
- rdev = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0, 0));
- if (!rdev)
- return 0;
-
mmd_address = get_mmd_address(pdata, mmd_reg);
/* The PCS registers are accessed using mmio. The underlying
@@ -1192,13 +1191,10 @@ static int xgbe_read_mmd_regs_v3(struct xgbe_prv_data *pdata, int prtad,
offset = get_index_offset(pdata, mmd_address, &index);
spin_lock_irqsave(&pdata->xpcs_lock, flags);
- pci_write_config_dword(rdev, 0x60, (pdata->xphy_base + pdata->xpcs_window_sel_reg));
- pci_write_config_dword(rdev, 0x64, index);
- pci_write_config_dword(rdev, 0x60, pdata->xphy_base + offset);
- pci_read_config_dword(rdev, 0x64, &mmd_data);
+ amd_smn_write(0, (pdata->smn_base + pdata->xpcs_window_sel_reg), index);
+ amd_smn_read(0, pdata->smn_base + offset, &mmd_data);
mmd_data = (offset % 4) ? FIELD_GET(XGBE_GEN_HI_MASK, mmd_data) :
FIELD_GET(XGBE_GEN_LO_MASK, mmd_data);
- pci_dev_put(rdev);
spin_unlock_irqrestore(&pdata->xpcs_lock, flags);
@@ -1209,13 +1205,8 @@ static void xgbe_write_mmd_regs_v3(struct xgbe_prv_data *pdata, int prtad,
int mmd_reg, int mmd_data)
{
unsigned int mmd_address, index, offset, ctr_mmd_data;
- struct pci_dev *rdev;
unsigned long flags;
- rdev = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0, 0));
- if (!rdev)
- return;
-
mmd_address = get_mmd_address(pdata, mmd_reg);
/* The PCS registers are accessed using mmio. The underlying
@@ -1230,10 +1221,9 @@ static void xgbe_write_mmd_regs_v3(struct xgbe_prv_data *pdata, int prtad,
offset = get_index_offset(pdata, mmd_address, &index);
spin_lock_irqsave(&pdata->xpcs_lock, flags);
- pci_write_config_dword(rdev, 0x60, (pdata->xphy_base + pdata->xpcs_window_sel_reg));
- pci_write_config_dword(rdev, 0x64, index);
- pci_write_config_dword(rdev, 0x60, pdata->xphy_base + offset);
- pci_read_config_dword(rdev, 0x64, &ctr_mmd_data);
+ amd_smn_write(0, (pdata->smn_base + pdata->xpcs_window_sel_reg), index);
+ amd_smn_read(0, pdata->smn_base + offset, &ctr_mmd_data);
+
if (offset % 4) {
ctr_mmd_data = FIELD_PREP(XGBE_GEN_HI_MASK, mmd_data) |
FIELD_GET(XGBE_GEN_LO_MASK, ctr_mmd_data);
@@ -1243,12 +1233,8 @@ static void xgbe_write_mmd_regs_v3(struct xgbe_prv_data *pdata, int prtad,
FIELD_GET(XGBE_GEN_LO_MASK, mmd_data);
}
- pci_write_config_dword(rdev, 0x60, (pdata->xphy_base + pdata->xpcs_window_sel_reg));
- pci_write_config_dword(rdev, 0x64, index);
- pci_write_config_dword(rdev, 0x60, (pdata->xphy_base + offset));
- pci_write_config_dword(rdev, 0x64, ctr_mmd_data);
- pci_dev_put(rdev);
-
+ amd_smn_write(0, (pdata->smn_base + pdata->xpcs_window_sel_reg), index);
+ amd_smn_write(0, (pdata->smn_base + offset), ctr_mmd_data);
spin_unlock_irqrestore(&pdata->xpcs_lock, flags);
}
diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-pci.c b/drivers/net/ethernet/amd/xgbe/xgbe-pci.c
index 5496980e1cc7..3e2a5bb694e7 100644
--- a/drivers/net/ethernet/amd/xgbe/xgbe-pci.c
+++ b/drivers/net/ethernet/amd/xgbe/xgbe-pci.c
@@ -122,6 +122,10 @@
#include "xgbe.h"
#include "xgbe-common.h"
+#ifdef CONFIG_X86
+#include <asm/amd_nb.h>
+#endif
+
static int xgbe_config_multi_msi(struct xgbe_prv_data *pdata)
{
unsigned int vector_count;
@@ -302,18 +306,17 @@ static int xgbe_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
pdata->xpcs_window_sel_reg = PCS_V2_WINDOW_SELECT;
break;
}
+ pci_dev_put(rdev);
/* Configure the PCS indirect addressing support */
if (pdata->vdata->xpcs_access == XGBE_XPCS_ACCESS_V3) {
reg = XP_IOREAD(pdata, XP_PROP_0);
- pdata->xphy_base = PCS_RN_SMN_BASE_ADDR +
- (PCS_RN_PORT_ADDR_SIZE * XP_GET_BITS(reg, XP_PROP_0, PORT_ID));
- pci_write_config_dword(rdev, 0x60, pdata->xphy_base + (pdata->xpcs_window_def_reg));
- pci_read_config_dword(rdev, 0x64, ®);
+ pdata->smn_base = PCS_RN_SMN_BASE_ADDR +
+ (PCS_RN_PORT_ADDR_SIZE * XP_GET_BITS(reg, XP_PROP_0, PORT_ID));
+ amd_smn_read(0, pdata->smn_base + (pdata->xpcs_window_def_reg), ®);
} else {
reg = XPCS32_IOREAD(pdata, pdata->xpcs_window_def_reg);
}
- pci_dev_put(rdev);
pdata->xpcs_window = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, OFFSET);
pdata->xpcs_window <<= 6;
diff --git a/drivers/net/ethernet/amd/xgbe/xgbe.h b/drivers/net/ethernet/amd/xgbe/xgbe.h
index dbb1faaf6185..ba45ab0adb8c 100644
--- a/drivers/net/ethernet/amd/xgbe/xgbe.h
+++ b/drivers/net/ethernet/amd/xgbe/xgbe.h
@@ -1061,7 +1061,7 @@ struct xgbe_prv_data {
struct device *dev;
struct platform_device *phy_platdev;
struct device *phy_dev;
- unsigned int xphy_base;
+ unsigned int smn_base;
/* Version related data */
struct xgbe_version_data *vdata;
--
2.34.1
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