netdev - Re: [PATCH 3/9] net: mdio: ipq4019: Enable GPIO reset for ipq5332 platform

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Message-ID: <c46e3e0c-2870-4025-b00e-a0cc5b2ffbc3@quicinc.com>
Date: Thu, 16 Nov 2023 19:29:52 +0800
From: Jie Luo <quic_luoj@...cinc.com>
To: Robert Marko <robert.marko@...tura.hr>
CC: Andrew Lunn <andrew@...n.ch>, <agross@...nel.org>, <andersson@...nel.org>,
        <konrad.dybcio@...aro.org>, <davem@...emloft.net>,
        <edumazet@...gle.com>, <kuba@...nel.org>, <pabeni@...hat.com>,
        <robh+dt@...nel.org>, <krzysztof.kozlowski+dt@...aro.org>,
        <conor+dt@...nel.org>, <hkallweit1@...il.com>, <linux@...linux.org.uk>,
        <linux-arm-msm@...r.kernel.org>, <netdev@...r.kernel.org>,
        <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        <quic_srichara@...cinc.com>
Subject: Re: [PATCH 3/9] net: mdio: ipq4019: Enable GPIO reset for ipq5332
 platform



On 11/16/2023 7:19 PM, Robert Marko wrote:
> On Thu, Nov 16, 2023 at 12:14 PM Jie Luo <quic_luoj@...cinc.com> wrote:
>>
>>
>>
>> On 11/15/2023 11:11 PM, Andrew Lunn wrote:
>>> On Wed, Nov 15, 2023 at 11:25:09AM +0800, Luo Jie wrote:
>>>> Before doing GPIO reset on the MDIO slave devices, the common clock
>>>> output to MDIO slave device should be enabled, and the related GCC
>>>> clocks also need to be configured.
>>>>
>>>> Because of these extra configurations, the MDIO bus level GPIO and
>>>> PHY device level GPIO can't be leveraged.
>>>
>>> Its not clear to me why the normal reset cannot be used. The MBIO bus
>>> driver can probe, setup the clocks, and then register the MDIO bus to
>>> the core. The core can then use the GPIO resets.
>>>
>>> What am i missing?
>>>
>>>        Andrew
>>
>> Hi Andrew,
>> Looks we can leverage the MDIO bus GPIO to reset qca8084 PHY, but the
>> mdio bus gpio only supports one GPIO number.
> 
> But, you can specify a PHY specific reset-gpio under the PHY subnode.
> However, you must specify the PHY ID via compatible then, please look at:
> https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/Documentation/devicetree/bindings/net/ethernet-phy.yaml?h=next-20231116#n36
> 
> I do this commonly when there are multiple reset GPIO-s for different ethernet
> PHY-s.
> 
> Regards,
> Robert

Got it, thanks Robert for the information, i will try the GPIO reset of
PHY DT node, and update it in the next patch set.

>>
>> Here are the reasons i put the GPIO reset here.
>> 1. Currently one MDIO bus instance only connects one qca8084 PHY as
>> MDIO slave device on IPQ5332 platform, since the MDIO address
>> occupied by qca8084. if the other type PHY also needs to use MDIO
>> bus GPIO reset, then we can't cover this case.
>>
>> 2. Before doing the GPIO reset on qca8084, we need to enable the clock
>> output to qca8084 by configuring eth_ldo_rdy register, and the mdio
>> bus->reset is called after the mdio bus level reset.
>>
>> 3. program the mdio address of qca8084 PHY and the initialization
>> configurations needed before the registers of qca8084 can be accessed.
>> if we take the PHY level GPIO reset for qca8084, there is no call point
>> to do the initialization configurations and programing PHY address in
>> the MDIO driver code.
>>
>> i will check the feasibility of taking the PHY level GPIO reset and do
>> the initial configurations in the PHY probe function.
>>
>> FYI, here is the sequence to bring up qca8084.
>> a. enable clock output to qca8084.
>> b. do gpio reset of qca8084.
>> c. customize MDIO address and initialization configurations.
>> d. the PHY ID can be acquired.
>>
>>
>> Thanks,
>> Jie.
> 
> 
>