netdev - Re: [PATCH v5 3/6] net: phy: at803x: add QCA8084 ethernet phy support

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Date: Mon, 20 Nov 2023 16:34:55 +0100
From: Andrew Lunn <andrew@...n.ch>
To: Jie Luo <quic_luoj@...cinc.com>
Cc: "Russell King (Oracle)" <linux@...linux.org.uk>, davem@...emloft.net,
	edumazet@...gle.com, kuba@...nel.org, pabeni@...hat.com,
	robh+dt@...nel.org, krzysztof.kozlowski+dt@...aro.org,
	conor+dt@...nel.org, hkallweit1@...il.com, corbet@....net,
	netdev@...r.kernel.org, devicetree@...r.kernel.org,
	linux-kernel@...r.kernel.org, linux-doc@...r.kernel.org
Subject: Re: [PATCH v5 3/6] net: phy: at803x: add QCA8084 ethernet phy support

> Hi Andrew,
> The interface mode 10G_QXGMII is a type of USXGMII-M, the other modes
> such as 20G-QXGMII, 20G-OXGMII...
> 
> As for the interface mode 10G-QXGMII, there is a multiplexer for 4 PHYs,
> then do 66bit/68bit encode in xpcs and pass to PMA, the link topology:
> quad PHY --- multiplexer ---XPCS --- PMA.
> the 10G-QXGMII interface block includes multiplexer, XPCS and PMA.
> 
> when the PHY works on SGMII mode, then there is no xpcs, the only fourth
> PHY of qca8084 can work on SGMII mode, the link topology:
> the fourth PHY --- PCS --- PMA, the SGMII block includes PCS and PMA.

What i missed is that you have two different PMA blocks. PHY4 can be
muxed to either the QXGMII PMA or the 2500BaseX PMA. This is not clear
in the commit message, and i think why you are getting questions about
how 2500BaseX can work over QXGMII. Please expand you commit message
to explain the architecture in more detail.

So, next question. How do you control what PMA PHY4 is connected to?
Is this going to be based on interface mode? QXGMII it is configured
to use the QXGMII PMA? SGMII, 1000BaseX, and 2500BaseX it is
configured to the other PMA?

> Here is a problem as Russell mentioned earlier, we need to know which PHY
> device is changing the link status when the 10G-QXGMII mode is used,
> since there are 4 PHYs, when one of them has the link change, there is no
> PHY device information passed to the PHYLINK, so the PCS driver don't
> which PHY is changing link status and 10G-QXGMII mode don't know which
> channel(mapped to PHY) should be configured.

This is the first time QXGMII has been seen in mainline, so its good
to explain the background.

Are you saying there is a USXGMII-M level link change status? The link
between the SoC and the PHY package is up/down? If it is down, all
four MAC-PHY links are down. If it is up, it is possible to carry
frames between the SoC and the PHY package, but maybe the PHYs
themselves are down?

Withing the four multiplex streams, is there a per stream link change
indication?

	Andrew