netdev - Re: [RFC] support built-in ethernet phy which needs some mmio accesses

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Message-ID: <e3337e9e-a53d-4480-9a99-4594625450a1@lunn.ch>
Date: Mon, 20 Nov 2023 16:54:48 +0100
From: Andrew Lunn <andrew@...n.ch>
To: Jisheng Zhang <jszhang@...nel.org>
Cc: HeinerKallweit <hkallweit1@...il.com>,
	Russell King <linux@...linux.org.uk>,
	"David S.Miller" <davem@...emloft.net>,
	Eric Dumazet <edumazet@...gle.com>,
	Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>,
	Conor Dooley <conor.dooley@...rochip.com>, netdev@...r.kernel.org,
	linux-riscv@...ts.infradead.org
Subject: Re: [RFC] support built-in ethernet phy which needs some mmio
 accesses

> Per my understanding of the vendor code, it reads calibration data from
> efuse

Linux should have an API for accessing efuse data. So please make use
of that.

What address space is

#define REG_EPHY_TOP_WRAP 0x03009800
#define REG_EPHY_BASE 0x03009000

in? Is this range dedicated to the PHY? Is it within the MAC address
space?

Does the datasheet describe the PHY pages? I'm wondering if you can
access the same registers via MDIO?

Where is the MDIO driver? Since this is integrated into the silicon,
it could be MDIO is not actually MDIO and is much faster. If you can
access the same registers via MIDO, that would be the cleaner way to
do it.

   Andrew