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Message-ID: <6aeb28f5-04c2-4723-9da2-d168025c307c@lunn.ch>
Date: Tue, 21 Nov 2023 17:00:53 +0100
From: Andrew Lunn <andrew@...n.ch>
To: Tomer Maimon <tmaimon77@...il.com>
Cc: davem@...emloft.net, edumazet@...gle.com, robh+dt@...nel.org,
krzysztof.kozlowski+dt@...aro.org, alexandre.torgue@...s.st.com,
peppe.cavallaro@...com, joabreu@...opsys.com,
mcoquelin.stm32@...il.com, avifishman70@...il.com,
tali.perry1@...il.com, joel@....id.au, andrew@...econstruct.com.au,
venture@...gle.com, yuenn@...gle.com, benjaminfair@...gle.com,
j.neuschaefer@....net, openbmc@...ts.ozlabs.org,
netdev@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org,
linux-stm32@...md-mailman.stormreply.com,
linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH v1 2/2] net: stmmac: Add NPCM support
> +void npcm_dwmac_pcs_init(struct npcm_dwmac *dwmac, struct device *dev,
> + struct plat_stmmacenet_data *plat_dat)
> +{
> + u16 val;
> +
> + iowrite16((u16)(SR_MII_CTRL >> 9), dwmac->reg + IND_AC_BA_REG);
> + val = ioread16(dwmac->reg + PCS_SR_MII_CTRL_REG);
> + val |= PCS_RST;
> + iowrite16(val, dwmac->reg + PCS_SR_MII_CTRL_REG);
> +
> + while (val & PCS_RST)
> + val = ioread16(dwmac->reg + PCS_SR_MII_CTRL_REG);
> +
> + val &= ~(PCS_AN_ENABLE);
> + iowrite16(val, dwmac->reg + PCS_SR_MII_CTRL_REG);
> +}
Is this a licensed PCS implementation? Or home grown? If its been
licensed from somebody, it maybe should live in driver/net/pcs, so
others can reuse it when they license the same core.
Andrew
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