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Message-ID: <cf62fefa-c746-4d20-8845-38e3475f0ed5@intel.com>
Date: Thu, 23 Nov 2023 11:34:32 +0100
From: Wojciech Drewek <wojciech.drewek@...el.com>
To: Furong Xu <0x1207@...il.com>
CC: "David S. Miller" <davem@...emloft.net>, Alexandre Torgue
<alexandre.torgue@...s.st.com>, Jose Abreu <joabreu@...opsys.com>, "Eric
Dumazet" <edumazet@...gle.com>, Jakub Kicinski <kuba@...nel.org>, Paolo Abeni
<pabeni@...hat.com>, Maxime Coquelin <mcoquelin.stm32@...il.com>, Joao Pinto
<jpinto@...opsys.com>, Simon Horman <horms@...nel.org>,
<netdev@...r.kernel.org>, <linux-stm32@...md-mailman.stormreply.com>,
<linux-arm-kernel@...ts.infradead.org>, <linux-kernel@...r.kernel.org>,
<xfr@...look.com>, <rock.xu@....com>
Subject: Re: [PATCH net v1] net: stmmac: xgmac: Disable FPE MMC interrupts
On 23.11.2023 11:24, Furong Xu wrote:
> On Thu, 23 Nov 2023 11:17:17 +0100
> Wojciech Drewek <wojciech.drewek@...el.com> wrote:
>
>> On 23.11.2023 10:35, Furong Xu wrote:
>>> Commit aeb18dd07692 ("net: stmmac: xgmac: Disable MMC interrupts
>>> by default") leaves the FPE(Frame Preemption) MMC interrupts enabled.
>>> Now we disable FPE TX and RX interrupts too.
>>
>> Hi,
>> Thanks for the patch, one question:
>> Why do we have to disable them?
>>
>
> The original commit aeb18dd07692 by Jose Abreu says:
>
> MMC interrupts were being enabled, which is not what we want because it
> will lead to a storm of interrupts that are not handled at all. Fix it
> by disabling all MMC interrupts for XGMAC.
I would add this information the commit message.
>
>>>
>>> Fixes: aeb18dd07692 ("net: stmmac: xgmac: Disable MMC interrupts by default")
>>> Signed-off-by: Furong Xu <0x1207@...il.com>
>>> ---
>>> drivers/net/ethernet/stmicro/stmmac/mmc_core.c | 4 ++++
>>> 1 file changed, 4 insertions(+)
>>>
>>> diff --git a/drivers/net/ethernet/stmicro/stmmac/mmc_core.c b/drivers/net/ethernet/stmicro/stmmac/mmc_core.c
>>> index ea4910ae0921..cdd7fbde2bfa 100644
>>> --- a/drivers/net/ethernet/stmicro/stmmac/mmc_core.c
>>> +++ b/drivers/net/ethernet/stmicro/stmmac/mmc_core.c
>>> @@ -177,8 +177,10 @@
>>> #define MMC_XGMAC_RX_DISCARD_OCT_GB 0x1b4
>>> #define MMC_XGMAC_RX_ALIGN_ERR_PKT 0x1bc
>>>
>>> +#define MMC_XGMAC_FPE_TX_INTR_MASK 0x204
>>> #define MMC_XGMAC_TX_FPE_FRAG 0x208
>>> #define MMC_XGMAC_TX_HOLD_REQ 0x20c
>>> +#define MMC_XGMAC_FPE_RX_INTR_MASK 0x224
>>> #define MMC_XGMAC_RX_PKT_ASSEMBLY_ERR 0x228
>>> #define MMC_XGMAC_RX_PKT_SMD_ERR 0x22c
>>> #define MMC_XGMAC_RX_PKT_ASSEMBLY_OK 0x230
>>> @@ -352,6 +354,8 @@ static void dwxgmac_mmc_intr_all_mask(void __iomem *mmcaddr)
>>> {
>>> writel(0x0, mmcaddr + MMC_RX_INTR_MASK);
>>> writel(0x0, mmcaddr + MMC_TX_INTR_MASK);
>>> + writel(MMC_DEFAULT_MASK, mmcaddr + MMC_XGMAC_FPE_TX_INTR_MASK);
>>> + writel(MMC_DEFAULT_MASK, mmcaddr + MMC_XGMAC_FPE_RX_INTR_MASK);
>>> writel(MMC_DEFAULT_MASK, mmcaddr + MMC_XGMAC_RX_IPC_INTR_MASK);
>>> }
>>>
>
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