netdev - RE: [EXT] [PATCH net] net: stmmac: update Rx clk divider for 10M SGMII

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Message-ID: 
 <SJ0PR18MB5216D3FDA9F68612A90E1F0DDBB8A@SJ0PR18MB5216.namprd18.prod.outlook.com>
Date: Fri, 24 Nov 2023 06:39:58 +0000
From: Suman Ghosh <sumang@...vell.com>
To: Sneh Shah <quic_snehshah@...cinc.com>, Vinod Koul <vkoul@...nel.org>,
        Bhupesh Sharma <bhupesh.sharma@...aro.org>,
        Alexandre Torgue
	<alexandre.torgue@...s.st.com>,
        Jose Abreu <joabreu@...opsys.com>,
        "David S.
 Miller" <davem@...emloft.net>,
        Eric Dumazet <edumazet@...gle.com>, Jakub
 Kicinski <kuba@...nel.org>,
        Paolo Abeni <pabeni@...hat.com>,
        Maxime Coquelin
	<mcoquelin.stm32@...il.com>,
        "netdev@...r.kernel.org"
	<netdev@...r.kernel.org>,
        "linux-arm-msm@...r.kernel.org"
	<linux-arm-msm@...r.kernel.org>,
        "linux-stm32@...md-mailman.stormreply.com"
	<linux-stm32@...md-mailman.stormreply.com>,
        "linux-arm-kernel@...ts.infradead.org"
	<linux-arm-kernel@...ts.infradead.org>,
        "linux-kernel@...r.kernel.org"
	<linux-kernel@...r.kernel.org>
CC: "kernel@...cinc.com" <kernel@...cinc.com>,
        Andrew Halaney
	<ahalaney@...hat.com>
Subject: RE: [EXT] [PATCH net] net: stmmac: update Rx clk divider for 10M
 SGMII

Hi Sneh,

>----------------------------------------------------------------------
>SGMII 10MBPS mode needs RX clock divider to avoid drops in Rx.
>Update configure SGMII function with rx clk divider programming.
>
[Suman] You need to add the Fixes tag as well.
>Signed-off-by: Sneh Shah <quic_snehshah@...cinc.com>
>---
> drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c | 3 +++
> 1 file changed, 3 insertions(+)
>
>diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
>b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
>index d3bf42d0fceb..f8c42e91a624 100644
>--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
>+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
>@@ -34,6 +34,7 @@
> #define RGMII_CONFIG_LOOPBACK_EN		BIT(2)
> #define RGMII_CONFIG_PROG_SWAP			BIT(1)
> #define RGMII_CONFIG_DDR_MODE			BIT(0)
>+#define RGMII_CONFIG_SGMII_CLK_DVDR		GENMASK(18, 10)
>
> /* SDCC_HC_REG_DLL_CONFIG fields */
> #define SDCC_DLL_CONFIG_DLL_RST			BIT(30)
>@@ -617,6 +618,8 @@ static int ethqos_configure_sgmii(struct qcom_ethqos
>*ethqos)
> 	case SPEED_10:
> 		val |= ETHQOS_MAC_CTRL_PORT_SEL;
> 		val &= ~ETHQOS_MAC_CTRL_SPEED_MODE;
>+		rgmii_updatel(ethqos, RGMII_CONFIG_SGMII_CLK_DVDR, BIT(10) |
>+			      GENMASK(15, 14), RGMII_IO_MACRO_CONFIG);
> 		break;
> 	}
>
>--
>2.17.1
>