lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Date: Tue, 28 Nov 2023 13:06:56 +0000
From: "Russell King (Oracle)" <>
To: Christian Marangi <>
Cc: Andrew Lunn <>, Heiner Kallweit <>,
	"David S. Miller" <>,
	Eric Dumazet <>,
	Jakub Kicinski <>, Paolo Abeni <>,
	Robert Marko <>,,, kernel test robot <>
Subject: Re: [net-next PATCH v2] net: phy: aquantia: drop wrong endianness
 conversion for addr and CRC

On Tue, Nov 28, 2023 at 01:44:39PM +0100, Christian Marangi wrote:
> Also the CRC returned from the mailbox CRC has to be converted with
> le16_to_cpu since it's LE and won't match on BE system. Am I wrong?

I think you are. As I've said before, everything transferred over the
MDIO bus is totally independent of the CPU endianness. Bit 0 in the
registers on the PHY will appear in bit 0 of the CPU register, and
bit 15 in the registers on the PHY will appear in bit 15 of the CPU

If this weren't the case, then if we access the BMCR register, and
the BMCR contains 0x1140 (indicating AN is enabled, full duplex,
1000Mbps) then if these were CPU endian-dependent, we'd end up reading
0x4011, and that will break phylib _and_ user applications (these
register definitions are exported to userspace.)

RMK's Patch system:
FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!

Powered by blists - more mailing lists