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Message-ID: <0a8be0185fe64398b85098cc7259c1c9@realtek.com>
Date: Wed, 29 Nov 2023 15:08:11 +0000
From: Hau <hau@...ltek.com>
To: Heiner Kallweit <hkallweit1@...il.com>
CC: nic_swsd <nic_swsd@...ltek.com>,
"davem@...emloft.net"
<davem@...emloft.net>,
"edumazet@...gle.com" <edumazet@...gle.com>,
"kuba@...nel.org" <kuba@...nel.org>,
"pabeni@...hat.com" <pabeni@...hat.com>,
"netdev@...r.kernel.org" <netdev@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"grundler@...omium.org" <grundler@...omium.org>,
"stable@...r.kernel.org"
<stable@...r.kernel.org>
Subject: RE: [PATCH net 1/2] r8169: enable rtl8125b pause slot
> > When FIFO reach near full state, device will issue pause frame.
> > If pause slot is enabled(set to 1), in this time, device will issue
> > pause frame once. But if pause slot is disabled(set to 0), device will
> > keep sending pause frames until FIFO reach near empty state.
> >
> > When pause slot is disabled, if there is no one to handle receive
> > packets (ex. unexpected shutdown), device FIFO will reach near full
> > state and keep sending pause frames. That will impact entire local
> > area network.
> >
> > In this patch default enable pause slot to prevent this kind of
> > situation.
> >
> Can this change have any side effect? I'm asking because apparently the hw
> engineers had a reason to make the behavior configurable.
It should not have any side effect. This setting is also used in Realtek driver.
> > Fixes: f1bce4ad2f1c ("r8169: add support for RTL8125")
> > Cc: stable@...r.kernel.org
> > Signed-off-by: ChunHao Lin <hau@...ltek.com>
> > ---
> > drivers/net/ethernet/realtek/r8169_main.c | 7 ++++++-
> > 1 file changed, 6 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/net/ethernet/realtek/r8169_main.c
> > b/drivers/net/ethernet/realtek/r8169_main.c
> > index 295366a85c63..473b3245754f 100644
> > --- a/drivers/net/ethernet/realtek/r8169_main.c
> > +++ b/drivers/net/ethernet/realtek/r8169_main.c
> > @@ -196,6 +196,7 @@ enum rtl_registers {
> > /* No threshold before first PCI xfer */
> > #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
> > #define RX_EARLY_OFF (1 << 11)
> > +#define RX_PAUSE_SLOT_ON (1 << 11)
>
> Depending on the chip version this bit has different meanings. Therefore it
> would be good to add a comment that RX_PAUSE_SLOT_ON is specific to
> RTL8125B.
I will do that and submit again.
> > #define RXCFG_DMA_SHIFT 8
> > /* Unlimited maximum PCI burst. */
> > #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
> > @@ -2305,9 +2306,13 @@ static void rtl_init_rxcfg(struct rtl8169_private
> *tp)
> > case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53:
> > RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN |
> RX_DMA_BURST | RX_EARLY_OFF);
> > break;
> > - case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63:
> > + case RTL_GIGA_MAC_VER_61:
> > RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST);
> > break;
> > + case RTL_GIGA_MAC_VER_63:
> > + RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST |
> > + RX_PAUSE_SLOT_ON);
> > + break;
> > default:
> > RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
> > break;
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