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Date: Thu, 30 Nov 2023 13:46:31 -0500
From: Min Li <lnimi@...mail.com>
To: richardcochran@...il.com,
	lee@...nel.org
Cc: linux-kernel@...r.kernel.org,
	netdev@...r.kernel.org,
	Min Li <min.li.xe@...esas.com>
Subject: [PATCH net-next v6 3/6] ptp: clockmatrix: Fix u8 -> u16, DPLL_WF_TIMER and DPLL_WP_TIMER are 2-byte registers

From: Min Li <min.li.xe@...esas.com>

Signed-off-by: Min Li <min.li.xe@...esas.com>
---
 drivers/ptp/ptp_clockmatrix.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/ptp/ptp_clockmatrix.c b/drivers/ptp/ptp_clockmatrix.c
index 6d55da54e496..d069b6e451ef 100644
--- a/drivers/ptp/ptp_clockmatrix.c
+++ b/drivers/ptp/ptp_clockmatrix.c
@@ -1396,18 +1396,18 @@ static int idtcm_set_pll_mode(struct idtcm_channel *channel,
 	struct idtcm *idtcm = channel->idtcm;
 	int err;
 	u8 dpll_mode;
-	u8 timeout = 0;
+	u8 buf[2] = {0};
 
 	/* Setup WF/WP timer for phase pull-in to work correctly */
 	err = idtcm_write(idtcm, channel->dpll_n, DPLL_WF_TIMER,
-			  &timeout, sizeof(timeout));
+			  buf, sizeof(buf));
 	if (err)
 		return err;
 
 	if (mode == PLL_MODE_WRITE_PHASE)
-		timeout = 160;
+		buf[0] = 160;
 	err = idtcm_write(idtcm, channel->dpll_n, DPLL_WP_TIMER,
-			  &timeout, sizeof(timeout));
+			  buf, sizeof(buf));
 	if (err)
 		return err;
 
-- 
2.39.2


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