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Message-ID: <PH7PR03MB70645A63EA0D578001954977A082A@PH7PR03MB7064.namprd03.prod.outlook.com> Date: Thu, 30 Nov 2023 13:46:34 -0500 From: Min Li <lnimi@...mail.com> To: richardcochran@...il.com, lee@...nel.org Cc: linux-kernel@...r.kernel.org, netdev@...r.kernel.org, Min Li <min.li.xe@...esas.com> Subject: [PATCH net-next v6 6/6] ptp: clockmatrix: move register and firmware related definition to idt8a340_reg.h From: Min Li <min.li.xe@...esas.com> This change is needed by rsmu driver, which will be submitted separately from mfd tree. Signed-off-by: Min Li <min.li.xe@...esas.com> --- drivers/ptp/ptp_clockmatrix.h | 33 --------- include/linux/mfd/idt8a340_reg.h | 121 +++++++++++++++++++++++++++++-- 2 files changed, 113 insertions(+), 41 deletions(-) diff --git a/drivers/ptp/ptp_clockmatrix.h b/drivers/ptp/ptp_clockmatrix.h index 31d90b1bf025..f041c7999ddc 100644 --- a/drivers/ptp/ptp_clockmatrix.h +++ b/drivers/ptp/ptp_clockmatrix.h @@ -21,32 +21,6 @@ #define MAX_ABS_WRITE_PHASE_NANOSECONDS (107374182L) #define MAX_FFO_PPB (244000) -#define TOD_MASK_ADDR (0xFFA5) -#define DEFAULT_TOD_MASK (0x04) - -#define SET_U16_LSB(orig, val8) (orig = (0xff00 & (orig)) | (val8)) -#define SET_U16_MSB(orig, val8) (orig = (0x00ff & (orig)) | (val8 << 8)) - -#define TOD0_PTP_PLL_ADDR (0xFFA8) -#define TOD1_PTP_PLL_ADDR (0xFFA9) -#define TOD2_PTP_PLL_ADDR (0xFFAA) -#define TOD3_PTP_PLL_ADDR (0xFFAB) - -#define TOD0_OUT_ALIGN_MASK_ADDR (0xFFB0) -#define TOD1_OUT_ALIGN_MASK_ADDR (0xFFB2) -#define TOD2_OUT_ALIGN_MASK_ADDR (0xFFB4) -#define TOD3_OUT_ALIGN_MASK_ADDR (0xFFB6) - -#define DEFAULT_OUTPUT_MASK_PLL0 (0x003) -#define DEFAULT_OUTPUT_MASK_PLL1 (0x00c) -#define DEFAULT_OUTPUT_MASK_PLL2 (0x030) -#define DEFAULT_OUTPUT_MASK_PLL3 (0x0c0) - -#define DEFAULT_TOD0_PTP_PLL (0) -#define DEFAULT_TOD1_PTP_PLL (1) -#define DEFAULT_TOD2_PTP_PLL (2) -#define DEFAULT_TOD3_PTP_PLL (3) - #define PHASE_PULL_IN_THRESHOLD_NS_DEPRECATED (150000) #define PHASE_PULL_IN_THRESHOLD_NS (15000) #define TOD_WRITE_OVERHEAD_COUNT_MAX (2) @@ -121,11 +95,4 @@ struct idtcm { ktime_t start_time; }; -struct idtcm_fwrc { - u8 hiaddr; - u8 loaddr; - u8 value; - u8 reserved; -} __packed; - #endif /* PTP_IDTCLOCKMATRIX_H */ diff --git a/include/linux/mfd/idt8a340_reg.h b/include/linux/mfd/idt8a340_reg.h index 13b36f4858b3..5aeb0820f876 100644 --- a/include/linux/mfd/idt8a340_reg.h +++ b/include/linux/mfd/idt8a340_reg.h @@ -116,16 +116,41 @@ #define OTP_SCSR_CONFIG_SELECT 0x0022 #define STATUS 0x2010c03c -#define DPLL0_STATUS 0x0018 -#define DPLL1_STATUS 0x0019 -#define DPLL2_STATUS 0x001a -#define DPLL3_STATUS 0x001b -#define DPLL4_STATUS 0x001c -#define DPLL5_STATUS 0x001d -#define DPLL6_STATUS 0x001e -#define DPLL7_STATUS 0x001f +#define IN0_MON_STATUS 0x0008 +#define IN1_MON_STATUS 0x0009 +#define IN2_MON_STATUS 0x000a +#define IN3_MON_STATUS 0x000b +#define IN4_MON_STATUS 0x000c +#define IN5_MON_STATUS 0x000d +#define IN6_MON_STATUS 0x000e +#define IN7_MON_STATUS 0x000f +#define IN8_MON_STATUS 0x0010 +#define IN9_MON_STATUS 0x0011 +#define IN10_MON_STATUS 0x0012 +#define IN11_MON_STATUS 0x0013 +#define IN12_MON_STATUS 0x0014 +#define IN13_MON_STATUS 0x0015 +#define IN14_MON_STATUS 0x0016 +#define IN15_MON_STATUS 0x0017 +#define DPLL0_STATUS 0x0018 +#define DPLL1_STATUS 0x0019 +#define DPLL2_STATUS 0x001a +#define DPLL3_STATUS 0x001b +#define DPLL4_STATUS 0x001c +#define DPLL5_STATUS 0x001d +#define DPLL6_STATUS 0x001e +#define DPLL7_STATUS 0x001f #define DPLL_SYS_STATUS 0x0020 #define DPLL_SYS_APLL_STATUS 0x0021 +#define DPLL0_REF_STATUS 0x0022 +#define DPLL1_REF_STATUS 0x0023 +#define DPLL2_REF_STATUS 0x0024 +#define DPLL3_REF_STATUS 0x0025 +#define DPLL4_REF_STATUS 0x0026 +#define DPLL5_REF_STATUS 0x0027 +#define DPLL6_REF_STATUS 0x0028 +#define DPLL7_REF_STATUS 0x0029 +#define DPLL_SYS_REF_STATUS 0x002a #define DPLL0_FILTER_STATUS 0x0044 #define DPLL1_FILTER_STATUS 0x004c #define DPLL2_FILTER_STATUS 0x0054 @@ -192,6 +217,25 @@ #define DPLL_CTRL_REG_0 0x0002 #define DPLL_CTRL_REG_1 0x0003 #define DPLL_CTRL_REG_2 0x0004 +#define DPLL_REF_PRIORITY_0 0x000f +#define DPLL_REF_PRIORITY_1 0x0010 +#define DPLL_REF_PRIORITY_2 0x0011 +#define DPLL_REF_PRIORITY_3 0x0012 +#define DPLL_REF_PRIORITY_4 0x0013 +#define DPLL_REF_PRIORITY_5 0x0014 +#define DPLL_REF_PRIORITY_6 0x0015 +#define DPLL_REF_PRIORITY_7 0x0016 +#define DPLL_REF_PRIORITY_8 0x0017 +#define DPLL_REF_PRIORITY_9 0x0018 +#define DPLL_REF_PRIORITY_10 0x0019 +#define DPLL_REF_PRIORITY_11 0x001a +#define DPLL_REF_PRIORITY_12 0x001b +#define DPLL_REF_PRIORITY_13 0x001c +#define DPLL_REF_PRIORITY_14 0x001d +#define DPLL_REF_PRIORITY_15 0x001e +#define DPLL_REF_PRIORITY_16 0x001f +#define DPLL_REF_PRIORITY_17 0x0020 +#define DPLL_REF_PRIORITY_18 0x0021 #define DPLL_MAX_FREQ_OFFSET 0x0025 #define DPLL_WF_TIMER 0x002c #define DPLL_WP_TIMER 0x002e @@ -450,6 +494,10 @@ #define OUTPUT_TDC_1 0x2010cd08 #define OUTPUT_TDC_2 0x2010cd10 #define OUTPUT_TDC_3 0x2010cd18 + +#define OUTPUT_TDC_CTRL_4 0x0006 +#define OUTPUT_TDC_CTRL_4_V520 0x0007 + #define INPUT_TDC 0x2010cd20 #define SCRATCH 0x2010cf50 @@ -668,6 +716,28 @@ #define DPLL_STATE_MASK (0xf) #define DPLL_STATE_SHIFT (0x0) +/* Bit definitions for the DPLL0_REF_STAT register */ +#define DPLL_REF_STATUS_MASK (0x1f) + +/* Bit definitions for the DPLL register */ +#define DPLL_REF_PRIORITY_ENABLE_SHIFT (0) +#define DPLL_REF_PRIORITY_REF_SHIFT (1) +#define DPLL_REF_PRIORITY_GROUP_NUMBER_SHIFT (6) + +/* Bit definitions for the IN0_MON_STATUS register */ +#define IN_MON_STATUS_LOS_SHIFT (0) +#define IN_MON_STATUS_NO_ACT_SHIFT (1) +#define IN_MON_STATUS_FFO_LIMIT_SHIFT (2) + +#define DEFAULT_PRIORITY_GROUP (0) +#define MAX_PRIORITY_GROUP (3) + +#define MAX_REF_PRIORITIES (19) + +#define MAX_ELECTRICAL_REFERENCES (16) + +#define NO_REFERENCE (0x1f) + /* * Return register address based on passed in firmware version */ @@ -778,4 +848,39 @@ enum scsr_tod_write_type_sel { SCSR_TOD_WR_TYPE_SEL_DELTA_MINUS = 2, SCSR_TOD_WR_TYPE_SEL_MAX = SCSR_TOD_WR_TYPE_SEL_DELTA_MINUS, }; + +/* firmware interface */ +struct idtcm_fwrc { + u8 hiaddr; + u8 loaddr; + u8 value; + u8 reserved; +} __packed; + +#define SET_U16_LSB(orig, val8) (orig = (0xff00 & (orig)) | (val8)) +#define SET_U16_MSB(orig, val8) (orig = (0x00ff & (orig)) | (val8 << 8)) + +#define TOD_MASK_ADDR (0xFFA5) +#define DEFAULT_TOD_MASK (0x04) + +#define TOD0_PTP_PLL_ADDR (0xFFA8) +#define TOD1_PTP_PLL_ADDR (0xFFA9) +#define TOD2_PTP_PLL_ADDR (0xFFAA) +#define TOD3_PTP_PLL_ADDR (0xFFAB) + +#define TOD0_OUT_ALIGN_MASK_ADDR (0xFFB0) +#define TOD1_OUT_ALIGN_MASK_ADDR (0xFFB2) +#define TOD2_OUT_ALIGN_MASK_ADDR (0xFFB4) +#define TOD3_OUT_ALIGN_MASK_ADDR (0xFFB6) + +#define DEFAULT_OUTPUT_MASK_PLL0 (0x003) +#define DEFAULT_OUTPUT_MASK_PLL1 (0x00c) +#define DEFAULT_OUTPUT_MASK_PLL2 (0x030) +#define DEFAULT_OUTPUT_MASK_PLL3 (0x0c0) + +#define DEFAULT_TOD0_PTP_PLL (0) +#define DEFAULT_TOD1_PTP_PLL (1) +#define DEFAULT_TOD2_PTP_PLL (2) +#define DEFAULT_TOD3_PTP_PLL (3) + #endif -- 2.39.2
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