netdev - Re: [PATCH 10/14] arm64: renesas: r9a08g045: Add Ethernet nodes

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Message-ID: <CAMuHMdW9Unpw7NQOGWd4SeFV8XgvRYTKTXnt9Tsagb3Q3U9tNA@mail.gmail.com>
Date: Fri, 1 Dec 2023 18:35:57 +0100
From: Geert Uytterhoeven <geert@...ux-m68k.org>
To: Claudiu <claudiu.beznea@...on.dev>
Cc: s.shtylyov@....ru, davem@...emloft.net, edumazet@...gle.com, 
	kuba@...nel.org, pabeni@...hat.com, robh+dt@...nel.org, 
	krzysztof.kozlowski+dt@...aro.org, conor+dt@...nel.org, linux@...linux.org.uk, 
	magnus.damm@...il.com, mturquette@...libre.com, sboyd@...nel.org, 
	linus.walleij@...aro.org, p.zabel@...gutronix.de, arnd@...db.de, 
	m.szyprowski@...sung.com, alexandre.torgue@...s.st.com, afd@...com, 
	broonie@...nel.org, alexander.stein@...tq-group.com, 
	eugen.hristev@...labora.com, sergei.shtylyov@...il.com, 
	prabhakar.mahadev-lad.rj@...renesas.com, biju.das.jz@...renesas.com, 
	linux-renesas-soc@...r.kernel.org, netdev@...r.kernel.org, 
	devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, 
	linux-arm-kernel@...ts.infradead.org, linux-clk@...r.kernel.org, 
	linux-gpio@...r.kernel.org, Claudiu Beznea <claudiu.beznea.uj@...renesas.com>
Subject: Re: [PATCH 10/14] arm64: renesas: r9a08g045: Add Ethernet nodes

Hi Claudiu,

On Mon, Nov 20, 2023 at 8:01 AM Claudiu <claudiu.beznea@...on.dev> wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@...renesas.com>
>
> Add Ethernet nodes available on RZ/G3S (R9A08G045).
>
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@...renesas.com>

Thanks for your patch!

> --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
> @@ -149,6 +149,38 @@ sdhi2: mmc@...20000 {
>                         status = "disabled";
>                 };
>
> +               eth0: ethernet@...30000 {
> +                       compatible = "renesas,r9a08g045-gbeth", "renesas,rzg2l-gbeth";
> +                       reg = <0 0x11c30000 0 0x10000>;
> +                       interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
> +                       interrupt-names = "mux", "fil", "arp_ns";
> +                       clocks = <&cpg CPG_MOD R9A08G045_ETH0_CLK_AXI>,
> +                                <&cpg CPG_MOD R9A08G045_ETH0_CLK_CHI>,
> +                                <&cpg CPG_MOD R9A08G045_ETH0_REFCLK>;
> +                       clock-names = "axi", "chi", "refclk";
> +                       resets = <&cpg R9A08G045_ETH0_RST_HW_N>;
> +                       power-domains = <&cpg>;

Perhaps add a default phy mode, like on other SoCs?

    phy-mode = "rgmii"';

Also missing:

    #address-cells = <1>;
    #size-cells = <0>;

> +                       status = "disabled";
> +               };

Same comments for eth1.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds