netdev - Re: [PATCH v2 01/11] clk: renesas: rzg2l-cpg: Check reset monitor registers

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Message-ID: <CAMuHMdWfh7U6WqAgO85bLwZDKWpMgmviNdNfKRYtcxs4VEXsgQ@mail.gmail.com>
Date: Wed, 13 Dec 2023 14:26:16 +0100
From: Geert Uytterhoeven <geert@...ux-m68k.org>
To: Claudiu <claudiu.beznea@...on.dev>
Cc: s.shtylyov@....ru, davem@...emloft.net, edumazet@...gle.com, 
	kuba@...nel.org, pabeni@...hat.com, robh+dt@...nel.org, 
	krzysztof.kozlowski+dt@...aro.org, conor+dt@...nel.org, 
	geert+renesas@...der.be, magnus.damm@...il.com, mturquette@...libre.com, 
	sboyd@...nel.org, linus.walleij@...aro.org, 
	prabhakar.mahadev-lad.rj@...renesas.com, biju.das.jz@...renesas.com, 
	linux-renesas-soc@...r.kernel.org, netdev@...r.kernel.org, 
	devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, 
	linux-clk@...r.kernel.org, linux-gpio@...r.kernel.org, 
	Claudiu Beznea <claudiu.beznea.uj@...renesas.com>
Subject: Re: [PATCH v2 01/11] clk: renesas: rzg2l-cpg: Check reset monitor registers

Hi Claudiu,

On Thu, Dec 7, 2023 at 8:08 AM Claudiu <claudiu.beznea@...on.dev> wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@...renesas.com>
>
> The hardware manual of both RZ/G2L and RZ/G3S specifies that the reset
> monitor registers need to be interrogated when the reset signals are
> toggled (chapters "Procedures for Supplying and Stopping Reset Signals"
> and "Procedure for Activating Modules"). Without this, there is a chance
> that different modules (e.g., Ethernet) to not be ready after their reset
> signal is toggled, leading to failures (on probe or resume from deep sleep
> states).
>
> The same indications are available for RZ/V2M for TYPE-B reset controls.
>
> Fixes: ef3c613ccd68 ("clk: renesas: Add CPG core wrapper for RZ/G2L SoC")
> Fixes: 8090bea32484 ("clk: renesas: rzg2l: Add support for RZ/V2M reset monitor reg")
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@...renesas.com>
> ---
>
> Changes in v2:
> - adapted for CPG versions with monbit (e.g., RZ/V2M)
> - added a fixes tag for RZ/V2M
> - fixed typos in commit description

Thanks for the update!

> --- a/drivers/clk/renesas/rzg2l-cpg.c
> +++ b/drivers/clk/renesas/rzg2l-cpg.c
> @@ -1416,12 +1416,27 @@ static int rzg2l_cpg_assert(struct reset_controller_dev *rcdev,
>         struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev);
>         const struct rzg2l_cpg_info *info = priv->info;
>         unsigned int reg = info->resets[id].off;
> -       u32 value = BIT(info->resets[id].bit) << 16;
> +       u32 mask = BIT(info->resets[id].bit);
> +       s8 monbit = info->resets[id].monbit;
> +       u32 value = mask << 16;
>
>         dev_dbg(rcdev->dev, "assert id:%ld offset:0x%x\n", id, CLK_RST_R(reg));
>
>         writel(value, priv->base + CLK_RST_R(reg));
> -       return 0;
> +
> +       if (info->has_clk_mon_regs) {
> +               reg = CLK_MRST_R(reg);
> +       } else if (monbit >= 0) {
> +               reg = CPG_RST_MON;
> +               mask = BIT(monbit);
> +       } else {
> +               /* Wait for at least one cyc le of the RCLK clock (@ ca. 32 kHz) */

cycle

Reviewed-by: Geert Uytterhoeven <geert+renesas@...der.be>
i.e. will queue in renesas-clk-for-v6.8 with the above fixed.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds