netdev - Re: [PATCH] net: phy: at803x: Improve hibernation support on start up

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <4148e039-9c36-cea4-5787-3e4f254e1728@bootlin.com>
Date: Fri, 15 Dec 2023 09:22:45 +0100 (CET)
From: Romain Gantois <romain.gantois@...tlin.com>
To: "Russell King (Oracle)" <linux@...linux.org.uk>
cc: Romain Gantois <romain.gantois@...tlin.com>, 
    Oleksij Rempel <o.rempel@...gutronix.de>, Wei Fang <wei.fang@....com>, 
    Marek Vasut <marex@...x.de>, 
    "netdev@...r.kernel.org" <netdev@...r.kernel.org>, 
    "David S. Miller" <davem@...emloft.net>, Andrew Lunn <andrew@...n.ch>, 
    Eric Dumazet <edumazet@...gle.com>, Heiner Kallweit <hkallweit1@...il.com>, 
    Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>, 
    kernel@...gutronix.de, linux-clk@...r.kernel.org, 
    Stephen Boyd <sboyd@...nel.org>, 
    Michael Turquette <mturquette@...libre.com>
Subject: Re: [PATCH] net: phy: at803x: Improve hibernation support on start
 up

On Thu, 14 Dec 2023, Russell King (Oracle) wrote:

> On Thu, Dec 14, 2023 at 09:13:58AM +0100, Romain Gantois wrote:
> > Hello Russell,
> > 
> > I've implemented and tested the general-case solution you proposed to this 
> > receive clock issue with stmmac drivers. The core of your suggestion is pretty 
> > much unchanged, I just added a phylink_pcs flag for standalone PCS drivers that 
> > also need to provide the receive clock.
> 
> So this affects the ability of PCS to operate correctly as well as MACs?
> Would you enlighten which PCS are affected, and what PCS <--> PHY link
> modes this is required for?

The affected hardware is the RZN1 GMAC1 that is found in the r9a06g032 SoC from 
Renesas. This MAC controller is internally connected to a custom PCS that
functions as a RGMII converter. This converter is handled by a standalone PCS 
driver that is already upstream, unlike the GMAC1 driver. So in hardware, the 
MAC/PHY links are organised this way:

    RZN1 GMAC1 <--[GMII]--> MII_CONV1 (internal) <--[RGMII]--> external PHY

The issue is that the RX clock from the external PHY has to be transmitted by 
the MII converter before it reaches GMAC1. Therefore, if the RZN1 PCS driver 
isn't configured to let the clock through before the stmmac GMAC1 driver 
initializes its hardware, then said initialization will fail with a vague DMA 
error.

To solve this, I added a flag to phylink_pcs and made the phylink core set it in 
phylink_validate_mac_and_pcs(). This gives the PCS driver a chance to check the 
flag in pcs_validate() and allow the clock through before the GMAC1 net device 
is brought up.

Regards,

-- 
Romain Gantois, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com