netdev - Re: [PATCH v6 5/9] net: stmmac: Add Loongson-specific register definitions

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Date: Mon, 18 Dec 2023 18:22:04 +0800
From: Yanteng Si <siyanteng@...ngson.cn>
To: Andrew Lunn <andrew@...n.ch>
Cc: hkallweit1@...il.com, peppe.cavallaro@...com,
 alexandre.torgue@...s.st.com, joabreu@...opsys.com, fancer.lancer@...il.com,
 Jose.Abreu@...opsys.com, chenhuacai@...ngson.cn, linux@...linux.org.uk,
 guyinggang@...ngson.cn, netdev@...r.kernel.org, loongarch@...ts.linux.dev,
 chris.chenfeiyang@...il.com
Subject: Re: [PATCH v6 5/9] net: stmmac: Add Loongson-specific register
 definitions


在 2023/12/16 23:47, Andrew Lunn 写道:
> On Wed, Dec 13, 2023 at 06:14:23PM +0800, Yanteng Si wrote:
>> There are two types of Loongson DWGMAC. The first type shares the same
>> register definitions and has similar logic as dwmac1000. The second type
>> uses several different register definitions.
>>
>> Simply put, we split some single bit fields into double bits fileds:
>>
>> DMA_INTR_ENA_NIE = 0x00040000 + 0x00020000
>> DMA_INTR_ENA_AIE = 0x00010000 + 0x00008000
>> DMA_STATUS_NIS = 0x00040000 + 0x00020000
>> DMA_STATUS_AIS = 0x00010000 + 0x00008000
>> DMA_STATUS_FBI = 0x00002000 + 0x00001000
> What is missing here is why? What are the second bits used for? And

We think it is necessary to distinguish rx and tx, so we split these 
bits into two.

this is:

DMA_INTR_ENA_NIE = rx + tx

> why does the driver not care which bit is set when handing interrupts?

We will care about it later. Because now we will support the minimum 
feature set

first, which can reduce everyone’s review pressure.


Thanks,

Yanteng

>
>      Andrew