netdev - Re: [PATCH v8 14/14] dt-bindings: net: ar803x: add qca8084 PHY properties

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Message-ID: <7638f650-cf8c-4245-a28f-b1a9edf33c38@quicinc.com>
Date: Mon, 18 Dec 2023 11:27:34 +0800
From: Jie Luo <quic_luoj@...cinc.com>
To: Andrew Lunn <andrew@...n.ch>
CC: <davem@...emloft.net>, <edumazet@...gle.com>, <kuba@...nel.org>,
        <pabeni@...hat.com>, <robh+dt@...nel.org>,
        <krzysztof.kozlowski+dt@...aro.org>, <conor+dt@...nel.org>,
        <hkallweit1@...il.com>, <linux@...linux.org.uk>, <corbet@....net>,
        <p.zabel@...gutronix.de>, <f.fainelli@...il.com>,
        <netdev@...r.kernel.org>, <devicetree@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>, <linux-doc@...r.kernel.org>
Subject: Re: [PATCH v8 14/14] dt-bindings: net: ar803x: add qca8084 PHY
 properties



On 12/17/2023 1:30 AM, Andrew Lunn wrote:
>> The following is the chip package, the chip can work on the switch mode
>> like the existed upstream code qca8k, where PHY1-PHY4 is connected with
>> MAC1-MAC4 directly; The chip can also work on the PHY mode, where PHY1-
>> PHY4 is connected with PCS1 by 10g-qxgmii; Either switch mode or PHY mode,
>> the PHY4 is optionally connected with PCS0 by SGMII, PCS0 and PCS1
>> are connected with the SoC(IPQ platform) PCSes.
> 
> I don't really understand. Are you saying the hardware is actually :
> 
> 
> +----------------------------------------------+
> |          PCS1           PCS0                 |
> |                                              |
> |          MAC0           MAC5                 |
> |           |              |                   |
> |     +-----+--------------+-------------+     |
> |     |                                  |     |
> |     |                Switch            |     |
> |     |                                  |     |
> |     +-+---------+---------+---------+--+     |
> |       |         |         |         |        |
> |      MAC1      MAC2      MAC3      MAC4      |
> |                                              |
> |      PHY1      PHY2      PHY3      PHY4      |
> +----------------------------------------------+
> 

Actually there are two CHIP types, ,let me explain to be more clear.

1. The diagram you describe is actually the switch work mode, which has
the different chip name called qca8386, the DSA driver and PHY driver
are used, since the general PHY driver can't work for the PHY here.

  +----------------------------------------------+
  | +-----+
  | | GCC |
  | +-----+  PCS1           PCS0                 |
  |                                              |
  |          MAC0           MAC5                 |
  |           |              |                   |
  |     +-----+--------------+-------------+     |
  |     |                                  |     |
  |     |                Switch            |     |
  |     |                                  |     |
  |     +-+---------+---------+---------+--+     |
  |       |         |         |         |        |
  |      MAC1      MAC2      MAC3      MAC4      |
  |                                              |
  |      PHY1      PHY2      PHY3      PHY4      |
  +----------------------------------------------+

2. The pure PHY chip called by qca8084 works on the PHY mode 10-qxgmii
on quad-phy, or the sgmii mode can be configured on PHY4 optionally.
The qca8084 is below, there is no MAC involved on qca8084.

  +----------------------------------------------+
  |          PCS1           PCS0                 |
  |                                              |
  |   +-----+
  |   | GCC |
  |   +-----+
  |                                              |
  |      PHY1      PHY2      PHY3      PHY4      |
  +----------------------------------------------+

On qca8386, the same qca8084 PHY is used, but the qca8084 PHY is
connected with internal MAC directly same as qca8337(qca8k dsa driver).

On both Ethernet chips qca8386 and qca8084, GCC block is same and
with the same clock controller driver that provides the clocks and
resets used by the qca8084 PHY driver and qca8386 DSA driver(leverage
the existed DSA driver qca8k.c).

> When in PHY mode, the switch is hard coded to map the 4 PCS1 channels
> straight to MAC1-MAC4 and all switch functionality is disabled. But
> then in switch mode, the switch can be controlled as a DSA switch? The
> 10G PCS1 is then a single 10G port, not 4x 2.5G?

For the qca8084 PHY chip, there is no MAC involved, the PHY is connected 
with the PCS with 10g-qxgmii, PHY4 is optional connected with sgmii.

For the qca8386 switch chip, it is controlled as DSA, the PCS is
connected with the SOC(such as IPQ5332) PCS.
> 
> Is there a product brief for this PHY? That might help us understand
> this hardware?
> 
Sorry, i also searched it on the internet and Qualcomm website, there is
no Doc found, the CHIP is developed recently 1-2 year before, the Doc is
not updated to the website.

>      Andrew