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Message-ID: <06aae775-4d62-4cca-9152-f752a8f9a33a@quicinc.com>
Date: Wed, 3 Jan 2024 21:25:40 +0800
From: Jie Luo <quic_luoj@...cinc.com>
To: Bryan O'Donoghue <bryan.odonoghue@...aro.org>, <agross@...nel.org>,
<andersson@...nel.org>, <konrad.dybcio@...aro.org>,
<davem@...emloft.net>, <edumazet@...gle.com>, <kuba@...nel.org>,
<pabeni@...hat.com>, <robh+dt@...nel.org>,
<krzysztof.kozlowski+dt@...aro.org>, <conor+dt@...nel.org>,
<andrew@...n.ch>, <hkallweit1@...il.com>, <linux@...linux.org.uk>,
<robert.marko@...tura.hr>
CC: <linux-arm-msm@...r.kernel.org>, <netdev@...r.kernel.org>,
<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<quic_srichara@...cinc.com>
Subject: Re: [PATCH v4 2/5] net: mdio: ipq4019: enable the SoC uniphy clocks
for ipq5332 platform
On 1/3/2024 5:48 PM, Bryan O'Donoghue wrote:
> On 25/12/2023 08:44, Luo Jie wrote:
>> On the platform ipq5332, the related SoC uniphy GCC clocks need
>> to be enabled for making the MDIO slave devices accessible.
>>
>> These UNIPHY clocks are from the SoC platform GCC clock provider,
>> which are enabled for the connected PHY devices working.
>>
>> Signed-off-by: Luo Jie <quic_luoj@...cinc.com>
>> ---
>> drivers/net/mdio/mdio-ipq4019.c | 75 ++++++++++++++++++++++++++++-----
>> 1 file changed, 64 insertions(+), 11 deletions(-)
>>
>> diff --git a/drivers/net/mdio/mdio-ipq4019.c
>> b/drivers/net/mdio/mdio-ipq4019.c
>> index 5273864fabb3..e24b0e688b10 100644
>> --- a/drivers/net/mdio/mdio-ipq4019.c
>> +++ b/drivers/net/mdio/mdio-ipq4019.c
>> @@ -35,15 +35,36 @@
>> /* MDIO clock source frequency is fixed to 100M */
>> #define IPQ_MDIO_CLK_RATE 100000000
>> +/* SoC UNIPHY fixed clock */
>> +#define IPQ_UNIPHY_AHB_CLK_RATE 100000000
>> +#define IPQ_UNIPHY_SYS_CLK_RATE 24000000
>> +
>> #define IPQ_PHY_SET_DELAY_US 100000
>> /* Maximum SOC PCS(uniphy) number on IPQ platform */
>> #define ETH_LDO_RDY_CNT 3
>> +enum mdio_clk_id {
>> + MDIO_CLK_MDIO_AHB,
>> + MDIO_CLK_UNIPHY0_AHB,
>> + MDIO_CLK_UNIPHY0_SYS,
>> + MDIO_CLK_UNIPHY1_AHB,
>> + MDIO_CLK_UNIPHY1_SYS,
>> + MDIO_CLK_CNT
>> +};
>> +
>> struct ipq4019_mdio_data {
>> void __iomem *membase;
>> void __iomem *eth_ldo_rdy[ETH_LDO_RDY_CNT];
>> - struct clk *mdio_clk;
>> + struct clk *clk[MDIO_CLK_CNT];
>> +};
>> +
>> +static const char *const mdio_clk_name[] = {
>> + "gcc_mdio_ahb_clk",
>> + "uniphy0_ahb",
>> + "uniphy0_sys",
>> + "uniphy1_ahb",
>> + "uniphy1_sys"
>> };
>> static int ipq4019_mdio_wait_busy(struct mii_bus *bus)
>> @@ -209,14 +230,43 @@ static int ipq4019_mdio_write_c22(struct mii_bus
>> *bus, int mii_id, int regnum,
>> static int ipq_mdio_reset(struct mii_bus *bus)
>> {
>> struct ipq4019_mdio_data *priv = bus->priv;
>> - int ret;
>> + unsigned long rate;
>> + int ret, index;
>> - /* Configure MDIO clock source frequency if clock is specified in
>> the device tree */
>> - ret = clk_set_rate(priv->mdio_clk, IPQ_MDIO_CLK_RATE);
>> - if (ret)
>> - return ret;
>> + /* For the platform ipq5332, there are two SoC uniphies available
>> + * for connecting with ethernet PHY, the SoC uniphy gcc clock
>> + * should be enabled for resetting the connected device such
>> + * as qca8386 switch, qca8081 PHY or other PHYs effectively.
>> + *
>> + * Configure MDIO/UNIPHY clock source frequency if clock instance
>> + * is specified in the device tree.
>> + */
>> + for (index = MDIO_CLK_MDIO_AHB; index < MDIO_CLK_CNT; index++) {
>
> you could do a
>
> if (!priv->clk[index])
> continue;
Thanks for the comments, will update it.
>
> here and save a few cycles executing code for absent clocks. ipq6018 has
> just 1/5 of the clocks you are checking for here.
>
> Better still capture the number of clocks you find in probe() in a
> variable priv->num_clocks and only step through the array
Ok, thanks bod for the comments to improve the code.
>
> for (i = 0; i < priv->num_clocks; i++) {}
>
> ---
> bod
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