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Message-ID: <20240105130404.301172-4-gatien.chevallier@foss.st.com>
Date: Fri, 5 Jan 2024 14:03:54 +0100
From: Gatien Chevallier <gatien.chevallier@...s.st.com>
To: <Oleksii_Moisieiev@...m.com>, <gregkh@...uxfoundation.org>,
<herbert@...dor.apana.org.au>, <davem@...emloft.net>,
<robh+dt@...nel.org>, <krzysztof.kozlowski+dt@...aro.org>,
<conor+dt@...nel.org>, <alexandre.torgue@...s.st.com>,
<vkoul@...nel.org>, <jic23@...nel.org>, <olivier.moysan@...s.st.com>,
<arnaud.pouliquen@...s.st.com>, <mchehab@...nel.org>,
<fabrice.gasnier@...s.st.com>, <andi.shyti@...nel.org>,
<ulf.hansson@...aro.org>, <edumazet@...gle.com>, <kuba@...nel.org>,
<pabeni@...hat.com>, <hugues.fruchet@...s.st.com>, <lee@...nel.org>,
<will@...nel.org>, <catalin.marinas@....com>, <arnd@...nel.org>,
<richardcochran@...il.com>, Frank Rowand <frowand.list@...il.com>,
<peng.fan@....nxp.com>, <lars@...afoo.de>, <rcsekar@...sung.com>,
<wg@...ndegger.com>, <mkl@...gutronix.de>
CC: <linux-crypto@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-stm32@...md-mailman.stormreply.com>,
<linux-arm-kernel@...ts.infradead.org>, <linux-kernel@...r.kernel.org>,
<dmaengine@...r.kernel.org>, <linux-i2c@...r.kernel.org>,
<linux-iio@...r.kernel.org>, <alsa-devel@...a-project.org>,
<linux-media@...r.kernel.org>, <linux-mmc@...r.kernel.org>,
<netdev@...r.kernel.org>, <linux-phy@...ts.infradead.org>,
<linux-serial@...r.kernel.org>, <linux-spi@...r.kernel.org>,
<linux-usb@...r.kernel.org>,
Gatien Chevallier
<gatien.chevallier@...s.st.com>,
Rob Herring <robh@...nel.org>
Subject: [PATCH v9 03/13] dt-bindings: bus: document RIFSC
Document RIFSC (RIF security controller). RIFSC is a firewall controller
composed of different kinds of hardware resources.
Signed-off-by: Gatien Chevallier <gatien.chevallier@...s.st.com>
Reviewed-by: Rob Herring <robh@...nel.org>
---
Changes in V9:
- Added "simple-bus" to RIFSC's compatible list
- Added Rob's review tag
Changes in V6:
- Renamed access-controller to access-controllers
- Removal of access-control-provider property
- Removal of access-controller and access-controller-names
declaration in the patternProperties field. Add
additionalProperties: true in this field.
Changes in V5:
- Renamed feature-domain* to access-control*
Changes in V2:
- Corrected errors highlighted by Rob's robot
- No longer define the maxItems for the "feature-domains"
property
- Fix example (node name, status)
- Declare "feature-domain-names" as an optional
property for child nodes
- Fix description of "feature-domains" property
.../bindings/bus/st,stm32mp25-rifsc.yaml | 105 ++++++++++++++++++
1 file changed, 105 insertions(+)
create mode 100644 Documentation/devicetree/bindings/bus/st,stm32mp25-rifsc.yaml
diff --git a/Documentation/devicetree/bindings/bus/st,stm32mp25-rifsc.yaml b/Documentation/devicetree/bindings/bus/st,stm32mp25-rifsc.yaml
new file mode 100644
index 000000000000..20acd1a6b173
--- /dev/null
+++ b/Documentation/devicetree/bindings/bus/st,stm32mp25-rifsc.yaml
@@ -0,0 +1,105 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/bus/st,stm32mp25-rifsc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: STM32 Resource isolation framework security controller
+
+maintainers:
+ - Gatien Chevallier <gatien.chevallier@...s.st.com>
+
+description: |
+ Resource isolation framework (RIF) is a comprehensive set of hardware blocks
+ designed to enforce and manage isolation of STM32 hardware resources like
+ memory and peripherals.
+
+ The RIFSC (RIF security controller) is composed of three sets of registers,
+ each managing a specific set of hardware resources:
+ - RISC registers associated with RISUP logic (resource isolation device unit
+ for peripherals), assign all non-RIF aware peripherals to zero, one or
+ any security domains (secure, privilege, compartment).
+ - RIMC registers: associated with RIMU logic (resource isolation master
+ unit), assign all non RIF-aware bus master to one security domain by
+ setting secure, privileged and compartment information on the system bus.
+ Alternatively, the RISUP logic controlling the device port access to a
+ peripheral can assign target bus attributes to this peripheral master port
+ (supported attribute: CID).
+ - RISC registers associated with RISAL logic (resource isolation device unit
+ for address space - Lite version), assign address space subregions to one
+ security domains (secure, privilege, compartment).
+
+select:
+ properties:
+ compatible:
+ contains:
+ const: st,stm32mp25-rifsc
+ required:
+ - compatible
+
+properties:
+ compatible:
+ items:
+ - const: st,stm32mp25-rifsc
+ - const: simple-bus
+
+ reg:
+ maxItems: 1
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 1
+
+ ranges: true
+
+ "#access-controller-cells":
+ const: 1
+ description:
+ Contains the firewall ID associated to the peripheral.
+
+patternProperties:
+ "^.*@[0-9a-f]+$":
+ description: Peripherals
+ type: object
+
+ additionalProperties: true
+
+ required:
+ - access-controllers
+
+required:
+ - compatible
+ - reg
+ - "#address-cells"
+ - "#size-cells"
+ - "#access-controller-cells"
+ - ranges
+
+additionalProperties: false
+
+examples:
+ - |
+ // In this example, the usart2 device refers to rifsc as its domain
+ // controller.
+ // Access rights are verified before creating devices.
+
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ rifsc: bus@...80000 {
+ compatible = "st,stm32mp25-rifsc", "simple-bus";
+ reg = <0x42080000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ #access-controller-cells = <1>;
+ ranges;
+
+ usart2: serial@...e0000 {
+ compatible = "st,stm32h7-uart";
+ reg = <0x400e0000 0x400>;
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ck_flexgen_08>;
+ access-controllers = <&rifsc 32>;
+ };
+ };
--
2.35.3
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